FinFET with trench field plate

Patent metadata

Field	Value
Publication number	US-9698227-B2
Application number	US-201414584823-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Jul 11, 2012
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

First claim

What is claimed is:

1. A method of forming a fin field effect transistor (FinFET) device, the method comprising:
forming a trench in a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, the trench extending through an interface of the body portion and the drift region portion, opposing sidewalls of the trench being portions of the pad layer;
forming a gate in the trench and over a top surface of the pad layer, the gate comprising a gate dielectric and a gate electrode, the gate extending continuously along and directly contacts the opposing sidewalls and a bottom of the trench, the gate overlapping the interface of the body portion and the drift region portion;
depositing a dielectric material in the trench on opposing sides of the gate; and
embedding a first field plate in the dielectric material on a first side of the gate.

2. The method of claim 1 , further comprising forming a source along sidewalls of the trench.

3. The method of claim 2 , wherein the source extends along an upper surface of the body portion.

4. The method of claim 3 , wherein the source comprises dopants of the second doping type, the source having a higher concentration of the second doping type than the drift region portion.

5. The method of claim 1 , further comprising orienting a longest dimension of the trench orthogonal to a longest dimension of the gate.

6. The method of claim 1 , further comprising forming a second field plate in the dielectric material on a second side of the gate.

7. The method of claim 1 , wherein an upper surface of the first field plate is coplanar with an upper surface of the dielectric material.

8. The method of claim 1 , wherein the first field plate is spaced apart from the gate.

9. A method of forming a fin field effect transistor (FinFET) device, the method comprising:
forming a pad layer having a first portion having a first conductivity type and a second portion having a second conductivity type, the pad layer having a trench, the trench being in the first portion and the second portion, wherein the first portion extends to an upper surface of the pad layer and the second portion extends to the upper surface of the pad layer, wherein the first portion is a first continuous portion and the second portion is a second continuous portion, and wherein the trench is a single continuous trench;
forming a gate structure over the first portion and the second portion, the gate structure extending from a bottom of the trench to the upper surface of the pad layer;
forming a first source/drain region in the first portion, the first source/drain region having a second conductivity type; and
forming a dielectric material in the trench on opposing sides of the gate structure.

10. The method of claim 9 , further comprising forming a first field plate in the dielectric material in the trench in the second portion of the pad layer.

11. The method of claim 10 , wherein the first field plate is embedded in the dielectric material.

12. The method of claim 10 , further comprising forming a second field plate in the dielectric material in the trench in the first portion of the pad layer.

13. The method of claim 12 , where the first field plate and the second field plate are formed of polysilicon.

14. The method of claim 9 , wherein a dopant concentration of the second conductivity type in the first source/drain region is greater than a dopant concentration of the second conductivity type in the second portion.

15. A method of forming a fin field effect transistor (FinFET) device, the method comprising:
forming a first portion of a pad layer having dopants of a first conductivity type and a second portion of the pad layer having dopants of a second conductivity type, the pad layer being over an insulator layer, the dopants of the first conductivity type in the first portion extending to an upper surface of the pad layer, the dopants of the second conductivity type in the second portion extending to the upper surface of the pad layer;
forming a trench in the first portion and the second portion of the pad layer, the trench having a first sidewall, a second sidewall, and a bottom extending between the first sidewall and the second sidewall, the first sidewall comprising the first portion and the second portion, the second sidewall comprising the first portion and the second portion;
forming a gate structure extending along the first sidewall and the second sidewall of the trench, the gate structure overlying at least a part of the first portion and at least a part of the second portion;
forming a doped region along a sidewalls of the trench in the first portion, the doped region having dopants of the second conductivity type; and
forming a dielectric material in the trench on opposing sides of the gate structure.

16. The method of claim 15 , further comprising forming a first field plate in the dielectric material in the trench in the second portion of the pad layer.

17. The method of claim 16 , wherein the first field plate is laterally spaced apart from the gate structure.

18. The method of claim 16 , further comprising forming a second field plate in the dielectric material in the trench in the first portion of the pad layer.

19. The method of claim 18 , where the first field plate and the second field plate are formed of polysilicon.

20. The method of claim 15 , wherein a dopant concentration of the second conductivity type in the doped region is greater than a dopant concentration of the second conductivity type in the second portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ng Chun-Wai
• Chou Hsueh-Liang
• Su Po-Chih
• Liu Ruey-Hsin

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H01L29/7856

  Electricity · mapped topic

• H01L29/401 Primary

  Electricity · mapped topic

• H01L29/0684

  Electricity · mapped topic

• H01L29/7825

  Electricity · mapped topic