Semiconductor device

Patent metadata

Field	Value
Publication number	US-9698221-B2
Application number	US-201515307668-A
Country	US
Kind code	B2
Filing date	Mar 30, 2015
Priority date	May 1, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

It is an object to provide the techniques capable of restraining avalanche breakdown at cells opposite to a corner portion of a gate pad. A MOSFET is provided with a corner cell, which is disposed in a region opposite to a corner portion of a gate pad in a planar view, and an internal cell, which is disposed in a region in the opposite side of the gate pad with respect to the corner cell. In a contour shape of the corner cell, a longest distance among distances each of which is shortest distance between a longest side and each of sides opposite to the longest side is equal to or less than two times of a length of one of equal sides or a short side of the internal cell.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a gate pad;
a first cell disposed in a region opposite to a corner portion of said gate pad in a planar view; and
a second cell disposed in a region in an opposite side of said gate pad with respect to said first cell in the planar view; wherein
each of said first and second cells is provided with:
a semiconductor layer of a first conductivity type;
a base region of a second conductivity type formed in an upper portion of said semiconductor layer;
a gate electrode disposed via a gate insulating film in a trench penetrating said base region and reaching said semiconductor layer below said base region, said gate electrode having a pattern corresponding to a contour shape of said first and second cell in the planar view, and said gate electrode electrically connected to said gate pad; and
a protective diffusion layer of said second conductivity type formed in a bottom portion of said trench;
at least said second cell among said first and second cells is further provided with:
a source region of said first conductivity type formed in a part adjacent to said gate insulating film in an upper portion of said base region and
a source electrode electrically connected to said base region and said source region;
said contour shape of each of said first and second cells is a polygonal shape of a four-or-more sided polygon;
in said contour shape of said first cell, a longest distance among distances each of which is shortest distance between a longest side and each of sides opposite to said longest side is equal to or less than two times of a length of one of equal sides or a short side of said second cell; and
said polygonal shape of said first cell has more vertices than vertices of said polygonal shape of said second cell.

2. The semiconductor device according to claim 1 , wherein
all of interior angles of said polygonal shape of said first cell are 90° or more.

3. The semiconductor device according to claim 1 , wherein
said first cell is not provided with said source region.

4. The semiconductor device according to claim 1 , wherein
in said first cell, said source electrode is electrically insulated from said base region and said source region.

5. The semiconductor device according to claim 1 , wherein
said first cell is further provided with said source region and with said gate electrode and independently has a function of a switching element.

6. A semiconductor device comprising:
a gate pad;
a first cell disposed in a region opposite to a corner portion of said gate pad in a planar view;
a second cell disposed in a region in an opposite side of said gate pad with respect to said first cell in the planar view; and
a third cell disposed in a region opposite to a side portion of said gate pad in the planar view, said third cell having a side larger than a side of said second cell as a longest side; wherein
each of said first, second, and third cells is provided with:
a semiconductor layer of a first conductivity type;
a base region of a second conductivity type formed in an upper portion of said semiconductor layer;
a gate electrode disposed via a gate insulating film in a trench penetrating said base region and reaching said semiconductor layer below said base region, said gate electrode having a pattern corresponding to a contour shape of said first, second, and third cell in the planar view, and said gate electrode electrically connected to said gate pad; and
a protective diffusion layer of said second conductivity type formed in a bottom portion of said trench;
at least said second cell among said first, second, and third cells is further provided with:
a source region of said first conductivity type formed in a part adjacent to said gate insulating film in an upper portion of said base region and
a source electrode electrically connected to said base region and said source region;
said contour shape of each of said first, second, and third cells is a polygonal shape of a four-or-more sided polygon;
in said contour shape of said first cell, a longest distance among distances each of which is shortest distance between a longest side and each of sides opposite to said longest side is equal to or less than two times of a length of one of equal sides or a short side of said second cell; and
said polygonal shape of said first cell has more vertices than vertices of said polygonal shape of said second cell.

7. A semiconductor device comprising:
a gate pad;
a cell; and
an invalid region having none of said cell and serving as a region opposite to a corner portion of said gate pad in a planar view; wherein
said cells are provided with:
a semiconductor layer of a first conductivity type;
a base region of a second conductivity type formed in an upper portion of said semiconductor layer;
a gate electrode disposed via a gate insulating film in a first trench penetrating said base region and reaching said semiconductor layer below said base region, said gate electrode having a pattern corresponding to a contour shape of said cells in the planar view, and said gate electrode electrically connected to said gate pad;
a first protective diffusion layer of said second conductivity type formed in a bottom portion of said first trench;
a source region of said first conductivity type formed in a part adjacent to said gate insulating film in an upper portion of said base region; and
a source electrode electrically connected to said base region and said source region;
said invalid region is provided with a second protective diffusion layer of said second conductivity type formed in a bottom portion of a second trench penetrating said base region and reaching said semiconductor layer below said base region;
said second trench is wider than said first trench; and
a polygonal shape of a first cell among said cells has more vertices than vertices of a polygonal shape of a second cell among said cells.

8. The semiconductor device according to claim 1 , wherein
said semiconductor layer includes a wide-band-gap semiconductor.

9. The semiconductor device according to claim 1 , wherein
said corner portion of said gate pad includes a curved portion.

10. The semiconductor device according to claim 1 , wherein
said first cell has a larger area than said second cell.

11. The semiconductor device according to claim 6 , wherein
all of interior angles of said polygonal shape of said first cell are 90° or more.

12. The semiconductor device according to claim 6 , wherein
said first cell is not provided with said source region.

13. The semiconductor device according to claim 6 , wherein
in said first cell, said source electrode is electrically insulated from said base region and said source region.

14. The semiconductor device according to claim 6 , wherein
said first cell is further provided with said source region and with said gate electrode and independently has a function of a switching element.

15. The semiconductor device according to claim 6 , wherein
said semiconductor layer includes a wide-band-gap semiconductor.

16. The semiconductor device according to claim 6 , wherein
said corner portion of said gate pad includes a curved portion.

17. The semiconductor device according to claim 7 , wherein
said semiconductor layer includes a wide-band-gap semiconductor.

18. The semiconductor device according to claim 7 , wherein
said corner portion of said gate pad includes a curved portion.

Assignees

• Mitsubishi Electric Corp

Inventors

• Sugawara Katsutoshi
• Kagawa Yasuhiro
• Tanaka Rina
• Fukui Yutaka

Classifications

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H01L29/0865

  Electricity · mapped topic

• H01L29/0696 Primary

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic