Parallel bit line three-dimensional resistive random access memory

Patent metadata

Field	Value
Publication number	US-9698202-B2
Application number	US-201514635419-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Mar 2, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.

First claim

What is claimed is:

1. A memory device, comprising:
line stack structures located over a substrate, laterally spaced apart along a first horizontal direction, and extending along a second horizontal direction that is different from the first horizontal direction, each line stack structure comprising an alternating plurality of word lines and bit lines; and
a two-dimensional array of vertical selector lines that extend vertically, are laterally spaced from a neighboring line stack structure by a respective gate dielectric, and are spaced apart along the first horizontal direction and along the second horizontal direction,
wherein:
a memory material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines;
each memory material line structure comprises a material having at least two states having different bulk resistivity; and
each of the word lines and the bit lines within any line stack structure selected from the line stack structures continuously extends along the second horizontal direction,
wherein the memory device comprises at least one feature selected from:
a first feature that the memory device further comprises selector transistors configured to provide a switched electrical voltage to the two-dimensional array of vertical selector lines, and horizontal selector lines extending parallel to a top surface of the substrate, wherein the selector transistors are located between the horizontal selector lines and the two-dimensional array of the vertical selector lines, each select transistor configured to provide a switched electrical connection between a respective horizontal selector line and a respective vertical selector line, and wherein the horizontal selector lines extend along the first horizontal direction, and the selector transistors comprise selector gate electrode lines that extend along the second horizontal direction;
a second feature that the memory device further comprises selector transistors configured to provide a switched electrical voltage to the two-dimensional array of vertical selector lines, and horizontal selector lines extending parallel to a top surface of the substrate, wherein the selector transistors are located between the horizontal selector lines and the two-dimensional array of the vertical selector lines, each select transistor configured to provide a switched electrical connection between a respective horizontal selector line and a respective vertical selector line, wherein at least a subset of the selector transistors is located underneath a horizontal plane including a bottommost surface of the line stack structures;
a third feature that an entire set of word lines and bit lines within each line structure is spatially bounded between a pair of a respective first vertical plane and a respective second vertical plane that extend along the second horizontal direction and laterally spaced apart by a respective uniform width of the line structure along the first direction, the respective uniform width being less than a pitch of the two-dimensional array of vertical selector lines along the first horizontal direction, wherein an entirety of each line structure is spatially bounded between the pair of the respective first vertical plane and the respective second vertical plane, and each word line and each bit line within any line structure includes a respective first vertical sidewall located entirely within the respective first vertical plane and a respective second vertical sidewall located entirely within the respective second vertical plane;
a fourth feature that an entire set of word lines and bit lines within each line structure is spatially bounded between a pair of a respective first vertical plane and a respective second vertical plane that extend along the second horizontal direction and laterally spaced apart by a respective uniform width of the line structure along the first direction, the respective uniform width being less than a pitch of the two-dimensional array of vertical selector lines along the first horizontal direction, wherein an intervening line stack including the memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines;
a fifth feature that an entire set of word lines and bit lines within any line structure has a respective uniform width along the first horizontal direction throughout an entirety of the line structure, wherein the entire set of word lines and bit lines within any line structure has a respective same length along the second horizontal direction throughout the entirety of the line structure; and
a sixth feature that the line stack structures are arranged as a one-dimensional periodic array having a pitch along the first horizontal direction and laterally spaced from one another along the first horizontal direction, wherein a maximum lateral extent of each line stack structure along the first horizontal direction is less than the pitch of the one-dimensional periodic array along the first horizontal direction.

2. The memory device of claim 1 , wherein an intervening line stack including the memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines.

3. The memory device of claim 2 , wherein:
each surface portion of the intrinsic semiconductor material line structures that is located adjacent to a vertical selector line defines a vertical semiconductor channel; and
vertical electrical conduction through each vertical semiconductor channel is controlled by a respective vertical selector line.

4. The memory device of claim 2 , wherein the doped semiconductor material line structures comprise n-doped polysilicon, and the intrinsic semiconductor material line structures comprise intrinsic polysilicon.

5. The memory device of claim 1 , wherein each memory material line structure contacts a horizontal surface of a neighboring word line.

6. The memory device of claim 1 , wherein at least one word line within each line stack structure contacts an overlying memory material line structure and an underlying memory material line structure.

7. The memory device of claim 1 , wherein at least one bit line within each line stack structure contacts an overlying doped semiconductor material line structure and an underlying doped semiconductor material line structure.

8. The memory device of claim 1 , wherein the memory device comprises the first feature.

9. The memory device of claim 8 , wherein an entirety of each alternating plurality of word lines and bit lines has a uniform width throughout along the first horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

10. The memory device of claim 1 , wherein the memory structure comprises the second feature.

11. The memory device of claim 1 , wherein:
each word line located at a same level are structurally integrated as a finger of an integrated multifinger structure selected from a first integrated multifinger structure and a second integrated multifinger structure; and
the first integrated multifinger structure and the second integrated structure are disjoined from each other.

12. The memory device of claim 11 , wherein each gate dielectric contacts a sidewall of a finger of the fir

Assignees

• Sandisk 3D Llc
• Sandisk Technologies Llc

Inventors

• Takaki Seje

Classifications

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• H01L27/2481

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic