Film transistor array panel and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9698167-B2
Application number	US-201414534508-A
Country	US
Kind code	B2
Filing date	Nov 6, 2014
Priority date	Jul 15, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.

First claim

What is claimed is:

1. A thin film transistor array panel comprising:
a substrate including a display area and a peripheral area;
a first semiconductor layer disposed in the display area and a second semiconductor layer disposed on the peripheral area; and
a passivation layer disposed on the first semiconductor layer and the second semiconductor layer,
wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and
wherein a thickness of the first semiconductor layer is less than that of the second semiconductor layer.

2. The thin film transistor array panel of claim 1 , wherein
the second semiconductor layer is disposed on a gate driver area of the peripheral area.

3. The thin film transistor array panel of claim 2 , wherein
the second semiconductor layer includes a lower semiconductor layer and an upper semiconductor layer disposed on the lower semiconductor layer.

4. The thin film transistor array panel of claim 3 , wherein
the first semiconductor layer and the upper semiconductor layer of the second semiconductor lava are disposed as a same layer.

5. The thin film transistor array panel of claim 4 , wherein
the first semiconductor layer and the second semiconductor layer are formed with an oxide semiconductor including at least one of indium, gallium, and zinc.

6. The thin film transistor array panel of claim 5 , further comprising
a first gate electrode disposed on the substrate in the display area, and a first source electrode and a first drain electrode facing each other with respect to the first gate electrode, wherein
the first semiconductor layer is disposed between the first gate electrode and the first source electrode or between the first gate electrode and the first drain electrode.

7. The thin film transistor array panel of claim 6 , flintier comprising
a second gate electrode disposed on the substrate in the peripheral area, and a second source electrode and a second drain electrode facing each other with respect to the second gate electrode, wherein
the second semiconductor layer is disposed between the second gate electrode and the second source electrode or between the second gate electrode and the second drain electrode.

8. A method for manufacturing a thin film transistor array panel, comprising:
forming a first semiconductor layer in a display area and a second semiconductor layer in a peripheral area on a substrate including the display area and the peripheral area; and
forming a passivation layer on the first semiconductor layer and the second semiconductor layer,
wherein the first semiconductor layer and the second semiconductor layer are formed with an oxide semiconductor, and
wherein a thickness of the first semiconductor layer is formed to be less than that of the second semiconductor layer.

9. The method of claim 8 , further comprising:
disposing a shadow mask to correspond to the display area on the substrate;
forming a lower semiconductor material layer in the peripheral area while the shadow mask is disposed;
removing the shadow mask;
forming an upper semiconductor material layer on the lower semiconductor material layer in the peripheral area and forming a first semiconductor material layer in the display area while the shadow mask is removed; and
forming the first semiconductor layer and the second semiconductor layer by patterning the first semiconductor material layer, the upper semiconductor material layer, and the lower semiconductor material layer.

10. The method of claim 9 , wherein
the second semiconductor layer is formed on a gate driver area of the peripheral area.

11. The method of claim 10 , wherein
the first semiconductor layer and the upper semiconductor layer of the second semiconductor layer are formed as a same layer.

12. The method of claim 8 , wherein
the forming of a first semiconductor layer and a second semiconductor layer includes:
forming the semiconductor material layer with a same thickness in the display area and the peripheral area on the substrate; and
forming the first semiconductor layer a Id the second semiconductor layer having different thicknesses by etching the semiconductor material layer.

13. The method of claim 12 , wherein
the second semiconductor layer is formed on a gate driver area of the peripheral area.

14. The method of claim 8 , wherein
the first semiconductor layer and the second semiconductor layer are formed with an oxide semiconductor including at least one of indium, gallium, and zinc.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Doo Youl
• Kwon Hyuk Soon
• Kim Jang Soo

Classifications

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/427

  having different thicknesses of the semiconductor bodies in different TFTs · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title