Semiconductor device

Patent metadata

Field	Value
Publication number	US-9698154-B2
Application number	US-201615168349-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Aug 6, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A semiconductor device includes a substrate, a plurality of memory cell arrays, and an air gap structure. The substrate includes a cell region, a peripheral circuit region, and a boundary region. The boundary region is between the cell region and the peripheral circuit region. The plurality of memory cell arrays are on the cell region. The air gap structure includes a trench formed in the boundary region of the substrate. The air gap structure defines an air gap.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a cell region, a peripheral circuit region, and a boundary region,
the boundary region being between the cell region and the peripheral circuit region,

a plurality of memory cell arrays on the cell region, and
an air gap structure including a trench formed in the boundary region of the substrate, the air gap structure defining an air gap, wherein the air gap structure includes one of
a first air gap structure that is continuous, without being disconnected, to correspond to all of the plurality of memory cell arrays, the first air gap structure extending along sides of the plurality of memory cell arrays in a single direction,
a second air gap structure that includes a plurality of trenches that include the trench and are spaced apart from each other while having linear forms,
a third air gap structure that has a zigzag form when viewed from above, and
a fourth air gap structure that has a ladder form when viewed from above.

2. The semiconductor device of claim 1 , further comprising:
a plurality of air gap structures, wherein
each one of the air gap structures extends in a single direction along one side of a corresponding one of the memory cell arrays.

3. The semiconductor device of claim 2 , wherein a length of the air gap structures respectively corresponds to a length of the one side of each of the plurality of memory cell arrays.

4. The semiconductor device of claim 1 , wherein
the air gap structure includes the first air gap structure.

5. A semiconductor device comprising:
a substrate including a boundary region between a cell region and a peripheral circuit region, the boundary region including a trench;
a core logic circuit on the peripheral circuit region;
a plurality of memory cell arrays on the cell region, the plurality of memory cell arrays including a plurality of gate electrode layers stacked on the substrate and a plurality of channels extending substantially perpendicular to an upper surface of the substrate to penetrate through the plurality of gate electrode layers; and
an air gap structure defining an air gap in the trench formed in the boundary region.

6. The semiconductor device of claim 1 , wherein
the air gap structure includes the second air gap structure, and
depths of the plurality of trenches are equal to each other.

7. The semiconductor device of claim 1 , wherein
the air gap structure includes the second air gap structure, and
depths of the plurality of trenches are different from each other.

8. The semiconductor device of claim 1 , wherein the air gap structure includes the third air gap structure.

9. The semiconductor device of claim 1 , wherein the air gap structure includes the fourth air gap structure.

10. The semiconductor device of claim 1 , wherein the air gap structure is configured to limit heat from being transferred to the cell region from the peripheral circuit region.

11. The semiconductor device of claim 5 , wherein the air gap structure has a linear form.

12. The semiconductor device of claim 5 , further comprising:
a plurality of air gap structures, wherein
the plurality of air gap structures include the air gap structure,
the boundary region includes a plurality of trenches formed in the substrate,
the plurality of trenches include the trench,
each one of the air gap structures extends in a single direction along one side of a corresponding one of the memory cell arrays.

13. The semiconductor device of claim 5 , wherein the air gap structure has a zig zag form, or a ladder form, when viewed from above.

14. The semiconductor device of claim 5 , wherein the air gap structure includes an insulating layer in the trench, and the insulating layer defines the air gap.

15. The semiconductor device of claim 5 , wherein
the plurality of memory cell arrays each include a plurality of memory cell strings on the cell region of the substrate, and
the memory cell strings each include a plurality of memory cells stacked on top of each other between a ground selection transistor and a string selection transistor.

Assignees

• Lim Joon Sung
• Chang Kyu Baik
• Hur Sung Hoi
• Kim Woo Jung
• Samsung Electronics Co Ltd

Inventors

• Lim Joon Sung
• Chang Kyu Baik
• Hur Sung Hoi
• Kim Woo Jung

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H01L21/823878

  Electricity · mapped topic

• H01L27/11575 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic