Vertical memory devices

Patent metadata

Field	Value
Publication number	US-9698151-B2
Application number	US-201615179068-A
Country	US
Kind code	B2
Filing date	Jun 10, 2016
Priority date	Oct 8, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate;
a plurality of channels on the substrate, the channels extending in a first direction that is vertical to a top surface of the substrate;
a plurality of gate lines stacked on top of each other on the substrate, the gate lines surrounding the channels, the gate lines being spaced apart from each other along the first direction;
a plurality of wirings over the gate lines and electrically connected to the gate lines; and
an identification pattern on the substrate at the same level as a level of at least one of the wirings.

2. The vertical memory device of claim 1 , wherein
the gate lines at each level include a step portion extending in a second direction parallel to the top surface of the substrate, and
the wirings are electrically connected to the step portions of corresponding gate lines.

3. The vertical memory device of claim 1 , wherein
the wirings are disposed at a plurality of levels over the substrate, and
the identification pattern is at the same level as a level of a lowermost wiring of the wirings.

4. The vertical memory device of claim 1 , wherein
the wirings are disposed at a plurality of levels over the substrate, and
the identification pattern is disposed at the same level as a level of an uppermost wiring of the wirings.

5. The vertical memory device of claim 1 , wherein
the wirings are disposed at a plurality of levels over the substrate, and
the identification pattern is disposed at two or more levels of the plurality of the levels.

6. The vertical memory device of claim 1 , wherein the identification pattern includes one of a plurality of dot patterns, a plurality of line patterns, and a combination of a dot pattern and a line pattern.

7. The vertical memory device of claim 1 , wherein the identification pattern and the wirings include a conductive material that is the same.

8. The vertical memory device of claim 2 , wherein the identification pattern is spaced apart from the channels in the second direction with respect to the wirings.

9. The vertical memory device of claim 2 , further comprising:
a bit line extending in a third direction that is parallel to the top surface of the substrate and crosses the second direction, wherein
the bit line is connected to at least one of the channels, and
the identification pattern and the bit line are at the same level.

10. The vertical memory device of claim 8 , further comprising:
a dummy wiring on the substrate between the identification pattern and one of the wirings.

11. The vertical memory device of claim 9 , wherein the identification pattern is between the bit line and the wirings in a plan view.

12. The vertical memory device of claim 6 , wherein
the identification pattern includes the plurality of the line patterns, and
the line patterns cross each other.

13. A vertical memory device, comprising:
a substrate including a cell region, an extension region and a peripheral region;
a plurality of vertical channels on the cell region;
gate lines on the substrate, the gate lines surrounding the vertical channels, the gate lines stacked on top of each other on a top surface of the substrate, the gate lines extending over the cell region and the extension region;
contacts electrically connected to the gate lines on the extension region;
wirings electrically connected to the gate lines via the contacts, the wirings extending from the extension region to the peripheral region; and
an identification pattern on the substrate over an uppermost gate line of the gate lines.

14. The vertical memory device of claim 13 , wherein the identification pattern is at the same level above the substrate as a level of at least one of the wirings.

15. The vertical memory device of claim 13 , wherein
the vertical channels extend in a first direction that is vertical to a top surface of the substrate, and
the gate lines extend in a second direction and a third direction that are parallel to the top surface of the substrate and cross each other.

16. A vertical memory device, comprising:
a substrate including a cell region, extension region, and a peripheral region;
a cell block including,
gate lines stacked on top of each other, and
channels extending vertically through the gate lines;

an insulation layer on the cell block, the insulation layer extending over the cell region, the extension region, and the peripheral region; and
a conductive pattern on the insulation layer,
the conductive pattern including wirings and an identification pattern that are spaced apart each other on the insulation layer,
the wirings being electrically connected to the gate lines, and
the identification pattern being at the same level above the substrate as a level of the wirings.

17. The vertical memory device of claim 16 , wherein
the conductive pattern includes bit lines at the same level above the substrate as the wirings and the identification pattern,
the bit lines are electrically connected to the channels, and
the bit lines are spaced apart from the wirings and the identification pattern.

18. The vertical memory device of claim 16 , further comprising:
bit lines on the cell block; and
a second insulation layer on top of the bit lines and the insulation layer, wherein
the insulation layer is a first insulation layer, and
the conductive pattern is on top of the second insulation layer.

19. The vertical memory device of claim 16 , wherein the wirings and the identification pattern are formed of the same material.

20. The vertical memory device of claim 17 , wherein
the conductive pattern includes a dummy pattern,
the dummy pattern is spaced apart from the wirings and the identification pattern at the same level, and
the identification pattern is over the peripheral region.

Assignees

• Lee Seung-Min
• Cho Hoo-Sung
• NAM Jeong-Seok
• Lee Jong-Min
• Choi Yong-Joon
• Samsung Electronics Co Ltd

Inventors

• Lee Seung-Min
• Cho Hoo-Sung
• NAM Jeong-Seok
• Lee Jong-Min
• Choi Yong-Joon

Classifications

• H10W46/501

  for use before dicing · CPC title

• H10W46/401

  for identification or tracking · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title