Semiconductor device

US9698141B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9698141-B2
Application numberUS-201615062208-A
CountryUS
Kind codeB2
Filing dateMar 7, 2016
Priority dateSep 4, 2015
Publication dateJul 4, 2017
Grant dateJul 4, 2017

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  1. Title

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Abstract

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A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.

First claim

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What is claimed is: 1. A semiconductor device comprising: a first nitride semiconductor layer having a first region; a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon; a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region; a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer; a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region; a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region; a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode; a conductive substrate; a buffer layer between the conductive substrate and the first nitride semiconductor layer, the buffer layer having an electrical resistance higher than an electrical resistance of the conductive substrate; a first through electrode passing through the conductive substrate and the buffer layer and electrically connecting the first region and the source electrode; and a second through electrode passing through the fourth nitride semiconductor layer and electrically connecting the second region and the drain electrode. 2. The semiconductor device according to claim 1 , wherein the first nitride semiconductor layer and the third nitride semiconductor layer each includes a gallium nitride layer, and the second nitride semiconductor layer includes a gallium nitride layer containing carbon and silicon. 3. The semiconductor device according to claim 1 , further comprising: an electrical insulating region that surrounds the first region, the second region, and a part of the second nitride semiconductor layer between the first region and the second region. 4. The semiconductor device according to claim 1 , wherein the first region and the second region face each other. 5. The semiconductor device according to claim 1 , wherein the source electrode is electrically connected to the conductive substrate through a conductive wire. 6. The semiconductor device according to claim 1 , wherein the second through electrode is directly below the drain electrode. 7. The semiconductor device according to claim 1 , wherein the gate electrode is a gate of a field effect transistor, and the source and drain electrodes are respectively source and drain of the field effect transistor, and terminals of a Zener diode. 8. The semiconductor device according to claim 7 , further comprising: an electrical insulating region that surrounds the first region, the second region, and a part of the second nitride semiconductor layer between the first region and the second region to electrically isolate the field effect transistor from the Zener diode. 9. The semiconductor device according to claim 7 , wherein increasing a concentration of carbon impurity in the second nitride semiconductor layer increases the threshold voltage of the Zener diode. 10. The semiconductor device according to claim 7 , wherein decreasing a concentration of silicon impurity in the second nitride semiconductor layer increases the threshold voltage of the Zener diode. 11. A method of adjusting a breakdown voltage of a Zener diode that includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a first electrode of the Zener diode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, and a second electrode of the Zener diode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, said method comprising: increasing the concentration of carbon impurity in the second nitride semiconductor layer to increase the threshold voltage of the Zener diode. 12. The method according to claim 11 , wherein the first and second electrode are also respectively source and drain electrodes of a field effect transistor that includes a gate electrode on the fourth nitride semiconductor layer between the source electrode and the drain electrode. 13. The method according to claim 12 , wherein an electrical insulating region that surrounds the first region, the second region, and a part of the second nitride semiconductor layer between the first region and the second region is provided to electrically isolate the field effect transistor from the Zener diode. 14. A method of adjusting a breakdown voltage of a Zener diode that includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a first electrode of the Zener diode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, and a second electrode of the Zener diode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, said method comprising: decreasing the concentration of silicon impurity in the second nitride semiconductor layer to increase the threshold voltage of the Zener diode. 15. The semiconductor device according to claim 14 , wherein increasing the concentration of carbon impurity in the second nitride semiconductor layer to increase the threshold voltage of the Zener diode. 16. The method according to claim 14 , wherein the first and second electrode are also respectively source and drain electrodes of a field effect transistor that includes a gate electrode on the fourth nitride semiconductor layer between the source electrode and the drain electrode. 17. The method according to claim 16 , wherein an electrical insulating region that surrounds the first region, the second region, and a part of the second nitride semiconductor layer between the first region and the second region is provided to electrically isolate the field effect transistor from the Zener diode.

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What does patent US9698141B2 cover?
A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor laye…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H01L27/0629. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).