Power module with a plurality of patterns with convex and concave side

Patent metadata

Field	Value
Publication number	US-9698125-B2
Application number	US-201514863837-A
Country	US
Kind code	B2
Filing date	Sep 24, 2015
Priority date	Sep 30, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

First claim

What is claimed is:

1. A semiconductor device comprising:
a ceramic substrate having a first surface, and a second surface located on an opposite side of the first surface;
a plurality of metal patterns formed on the first surface of the ceramic substrate; and
a plurality of semiconductor chips mounted on one or more of the plurality of metal patterns,
wherein the plurality of metal patterns include:
a first metal pattern which has a first side and on which a plurality of first semiconductor chips among the plurality of semiconductor chips are mounted; and
a second metal pattern which has a second side facing the first side of the first metal pattern and which is separated from the first metal pattern,

wherein when seen in a plan view, the first side of the first metal pattern includes: a plurality of first convex portions protruding toward the second side of the second metal pattern; and a first concave portion formed between the plurality of first convex portions,
wherein when seen in a plan view, the second side of the second metal pattern includes: a second convex portion protruding toward the first side of the first metal pattern; and a plurality of second concave portions formed on both sides of the second convex portion,
wherein when seen in a plan view, the plurality of first convex portions are provided so as to respectively protrude toward the plurality of second concave portions, and the second convex portion is provided so as to protrude toward the first concave portion,
wherein the first surface of the ceramic substrate has: a first substrate side extending in a first direction; a second substrate side located on an opposite side of the first substrate side; a third substrate side extending in a second direction intersecting the first direction; and a fourth substrate side located on an opposite side of the third substrate side,
wherein each length of the first substrate side and the second substrate side is greater than each length of the third substrate side and the fourth substrate side, and
wherein each of the first side of the first metal pattern and the second side of the second metal pattern is provided along the first direction.

2. The semiconductor device according to claim 1 ,
wherein a first potential is supplied to the first metal pattern, and
a second potential which is different from the first potential is supplied to the second metal pattern.

3. The semiconductor device according to claim 1 ,
wherein, when seen in a plan view, the plurality of first convex portions are provided inside a region surrounded by the plurality of second concave portions, and the second convex portion is provided inside a region surrounded by the first concave portion.

4. The semiconductor device according to claim 3 ,
wherein at least one or more of the plurality of first semiconductor chips are electrically connected to the second metal pattern through a plurality of wires, and
each of the plurality of wires is bonded to the second convex portion of the second metal pattern.

5. The semiconductor device according to claim 4 ,
wherein an area of the second convex portion is greater than an area of each of the plurality of first convex portions.

6. The semiconductor device according to claim 1 ,
wherein the second metal pattern has a third side located on an opposite side of the second side,
the plurality of metal patterns include a third metal pattern which has a fourth side facing the third side of the second metal pattern and which is separated from the first metal pattern and the second metal pattern,
when seen in a plan view, the third side of the second metal pattern has a plurality of third convex portions protruding toward the fourth side of the third metal pattern and a third concave portion formed between the plurality of third convex portions,
when seen in a plan view, the fourth side of the third metal pattern has a fourth convex portion protruding toward the third side of the second metal pattern and a plurality of fourth concave portions formed on both sides of the fourth convex portion, and
the plurality of third convex portions are provided so as to protrude toward the plurality of fourth concave portions, and the fourth convex portion is provided so as to protrude toward the third concave portion.

7. The semiconductor device according to claim 6 ,
wherein the plurality of first convex portions are provided inside a region surrounded by the plurality of second concave portions, and the second convex portion is provided inside a region surrounded by the first concave portion.

8. The semiconductor device according to claim 7 ,
wherein at least one or more of the plurality of first semiconductor chips are electrically connected to the second metal pattern through a plurality of wires, and
each of the plurality of wires is bonded to the second convex portion of the second metal pattern.

9. The semiconductor device according to claim 8 ,
wherein an area of the second convex portion is greater than an area of each of the plurality of first convex portions.

10. The semiconductor device according to claim 6 ,
wherein the plurality of metal patterns include a plurality of fourth metal patterns arranged between the first substrate side of the ceramic substrate and the first metal pattern, and a plurality of fifth metal patterns arranged between the second substrate side of the ceramic substrate and the third metal pattern,
the first metal pattern has a fifth side which is located on an opposite side of the first side and which linearly extends along the first direction so as to face the plurality of fourth metal patterns,
the third metal pattern has a sixth side which is located on an opposite side of the fourth side and which linearly extends along the first direction so as to face the plurality of fifth metal patterns, and
a first virtual line connecting a center of the third substrate side and a center of the fourth substrate side of the ceramic substrate exists between the first side of the first metal pattern and the fourth side of the third metal pattern.

11. The semiconductor device according to claim 1 ,
wherein the plurality of metal patterns include:
the first metal pattern to which a first potential is supplied;
a third metal pattern to which a second potential lower than the first potential is supplied; and
a plurality of the second metal patterns which are provided between the first metal pattern and the third metal pattern, which are separated from each other, and to which a cyclically-changing potential is supplied,
a plurality of first semiconductor chips among the plurality of semiconductor chips are mounted on the first metal pattern,
a plurality of second semiconductor chips among the plurality of semiconductor chips are mounted on a plurality of the second metal pattern, respectively,
when seen in a plan view, in the first side of the first metal pattern, the plurality of first convex portions and a plurality of the first concave portions are alternately arranged, and
each of a plurality of the second metal patterns has the second convex portion of the second side protruding toward the first side of the first metal pattern and a plurality of the second concave portions formed on both sides of the second convex portion.

12. The semiconductor device according to claim 11 ,
wherein the plurality of first convex portions are provided inside a region surrounded by a plurality of the second concave portions, and a plurality of the second convex portions are provided inside a region surrounded by a plurality of the first concave portions.

13. The semiconductor device accordin

Assignees

• Renesas Electronics Corp

Inventors

• Sato Yukihiro
• Funatsu Katsuhiko
• Kanazawa Takamitsu
• Koido Masahiro
• Taya Hiroyoshi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W80/732

  having shape changed during the connecting · CPC title

• H10W76/47

  Solid or gel fillings · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title