Apparatus for stacked electronic circuitry and associated methods

Patent metadata

Field	Value
Publication number	US-9698123-B2
Application number	US-201113235166-A
Country	US
Kind code	B2
Filing date	Sep 16, 2011
Priority date	Sep 16, 2011
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

First claim

The invention claimed is:

1. An apparatus comprising:
a substrate comprising a non-metallic core having a plurality of vias formed therein, a dielectric layer on the non-metallic core, a metal layer on the dielectric layer, and a solder mask layer on the metal layer, wherein the metal layer has a surface, and a cavity is formed in the substrate that extends beyond the planar surface of the metal layer and through the solder mask layer;
a first die comprising electronic circuitry, the first die being disposed in the cavity in the substrate and attached to the substrate; and
a second die comprising electronic circuitry, wherein the second die is disposed above the first die, is electrically coupled to the first die, and is electrically coupled to the plurality of vias in the non-metallic core.

2. The apparatus according to claim 1 , wherein the cavity is formed in a surface of the substrate facing the second die.

3. The apparatus according to claim 2 , wherein the cavity has a depth of approximately 100 microns to approximately 300 microns.

4. The apparatus according to claim 1 , wherein the cavity has dimensions that fit the first die.

5. The apparatus according to claim 1 , wherein a top surface of the first die is co-planar with a top surface of the substrate.

6. The apparatus according to claim 1 , wherein the plurality of vias extend completely through the non-metallic core.

7. The apparatus according to claim 6 , wherein the first die is directly coupled to the second die via an interconnect.

8. The apparatus according to claim 7 , wherein the non-metallic core includes only a single planar surface that surround the cavity.

9. An electronic assembly comprising:
a first semiconductor die comprising electronic circuitry;
a substrate comprising a non-metallic core comprising a plurality of vias and having a planar surface, a dielectric layer on the planar surface of the non-metallic core, a metal layer on the dielectric layer, and a solder mask layer on the metal layer, wherein a cavity is formed in a first surface of the substrate and extends to the planar surface of the non-metallic core through the dielectric layer, the metal layer, and the solder mask layer, the cavity being dimensioned for the first semiconductor die to reside in the cavity and to be attached to the substrate;
a second semiconductor die comprising field programmable gate array (FPGA) circuitry, wherein the second semiconductor die is disposed above the first surface of the substrate, is bonded directly to the first semiconductor die via an interconnect, and is electrically coupled to the plurality of vias in the non-metallic core.

10. The electronic assembly according to claim 9 , wherein the electronic circuitry in the first semiconductor die comprises application specific integrated circuit (ASIC) circuitry.

11. The electronic assembly according to claim 9 , wherein the field programmable gate array (FPGA) circuitry comprises programmable interconnect circuitry, and wherein the programmable interconnect circuitry may be adapted to provide a configurable electrical interconnect between the first and second semiconductor die.

12. The electronic assembly according to claim 9 , wherein the cavity has a depth and wherein a top surface of the first semiconductor die is co-planar with the first surface of the substrate when the first semiconductor die is placed in the cavity.

13. The electronic assembly according to claim 9 , wherein the plurality of vias extend completely through the non-metallic core.

14. The electronic assembly according to claim 13 , further comprising:
a circuit carrier that is coupled to a given via of the plurality of vias, wherein the circuit carrier is disposed below the substrate.

Assignees

• Rahman Arifur
• Long Jon M
• Xie Yuanlin
• Altera Corp

Inventors

• Rahman Arifur
• Long Jon M
• Xie Yuanlin

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title