Semiconductor packages

Patent metadata

Field	Value
Publication number	US-9698088-B2
Application number	US-201615135364-A
Country	US
Kind code	B2
Filing date	Apr 21, 2016
Priority date	May 24, 2011
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first substrate;
a first semiconductor chip mounted on the first substrate;
a second substrate disposed on the first substrate, the second substrate including a central portion and a peripheral portion around the central portion;
a plurality of first connection members attached to the peripheral portion of the second substrate and configured to electrically connect the first and second substrates; and
a plurality of second connection members attached to the peripheral portion of the second substrate and configured to electrically connect the first and second substrates,
wherein the first semiconductor chip is under the central portion of the second substrate,
wherein only the first connection members are adjacent to a side of the central portion,
wherein only the second connection members are adjacent to a vertex of the central portion,
wherein each of the first connection members includes a first supporter and a first fusion conductive layer surrounding the first supporter, and
wherein each of the second connection members consists of a uniform conductive material.

2. The semiconductor package of claim 1 , wherein the central portion is disposed in a central area of a surface of the second substrate, and
wherein the peripheral portion is disposed in a peripheral area of the surface of the second substrate around the central area.

3. The semiconductor package of claim 1 , wherein the peripheral portion includes a center region and a corner region, the center region being adjacent to a central point of a side of the second substrate,
wherein the first connection members are attached to the center region of the peripheral portion, and
wherein the second connection members are attached to the corner region of the peripheral portion.

4. The semiconductor package of claim 1 , wherein each of the second connection members does not include the first supporter.

5. The semiconductor package of claim 1 , wherein each of the first connection members further includes a first adhesive layer disposed between the first supporter and the first fusion conductive layer, the first adhesive layer being a diffusion barrier layer to prevent diffusion from the first fusion conductive layer to the first supporter.

6. The semiconductor package of claim 1 , wherein each of the first connection members further includes a second supporter.

7. The semiconductor package of claim 1 , further comprising:
a plurality of central connection members attached to a central portion of the first semiconductor chip and interposed between the first substrate and the first semiconductor chip; and
a plurality of peripheral connection members attached to a peripheral portion of the first semiconductor chip and interposed between the first substrate and the first semiconductor chip,
wherein each of the central connection members includes a second supporter and a second fusion conductive layer surrounding the second supporter.

8. The semiconductor package of claim 7 , wherein a height of the first connection member is different from a height of the central connection member.

9. The semiconductor package of claim 1 , further comprising:
a plurality of central connection members attached to a central portion of a first surface of the first substrate; and
a plurality of peripheral connection members attached to a peripheral portion of the first surface of the first substrate,
wherein the first semiconductor chip mounted on a second surface opposite to the first surface, and
wherein each of the central connection members includes a second supporter and a second fusion conductive layer surrounding the second supporter.

10. The semiconductor package of claim 1 , further comprising a second semiconductor chip mounted on the second substrate,
wherein the second semiconductor chip is electrically connected to the second substrate through bonding wires.

11. The semiconductor package of claim 1 , wherein the first supporter includes a polymer material.

12. The semiconductor package of claim 1 , wherein a height of the first connection member is substantially equal to a height of the second connection member.

13. The semiconductor package of claim 1 , further comprising a mold layer encapsulating the first substrate and filling a space between the first substrate and the first semiconductor chip,
wherein a height of the first connection member is higher than a thickness of the mold layer.

14. The semiconductor package of claim 13 , wherein a plurality of holes penetrate the mold layer, and
wherein the first and second connection members are inserted into the holes.

15. A semiconductor package comprising:
a first substrate;
a first semiconductor chip mounted on the first substrate;
a second substrate disposed on the first substrate, the second substrate including a central portion;
a plurality of first connection members attached to a first region of the central portion of the second substrate and configured to electrically connect the first and second substrates; and
a plurality of second connection members attached to at least one of the peripheral portions of the second substrate and configured to electrically connect the first and second substrates,
wherein a cross shaped region is formed that consists of only the first connection members and the central region, and wherein all of the second connection members are located at peripheral portions around and outside of the cross shaped region,
wherein the first semiconductor chip is under a second region of the central portion of the second substrate,
wherein each of the first connection members includes a first supporter and a first fusion conductive layer surrounding the first supporter, and
wherein each of the second connection members consists of a uniform conductive material.

16. The semiconductor package of claim 15 , wherein the first and second connection members are spaced apart from the second region of the central portion of the second substrate.

17. A semiconductor package comprising:
a first sub semiconductor package including a first substrate and a first semiconductor chip mounted on a top surface of the first substrate;
a second sub semiconductor package on the first sub semiconductor package, the second sub semiconductor package including a second substrate and a second semiconductor chip mounted on a top surface of the second substrate;
a plurality of central connection members attached to a central portion of the first semiconductor chip and configured to electrically connect the first substrate and the first semiconductor chip, each of the central connection members includes a first supporter and fusion conductive layer surrounding the first supporter;
a plurality of peripheral connection members attached to a peripheral portion of the first semiconductor chip and configured to electrically connect the first substrate and the first semiconductor chip, each of the plurality of peripheral connection members consisting of a uniform conductive material;
a plurality of first connection members attached to a peripheral portion of the second substrate and configured to electrically connect the first and second substrates, each of the first connection members including a second supporter and a second fusion conductive layer surrounding the second supporter; and
a plurality of second connection members attached to the peripheral portion of the second substrate and configured to electrically connect the first and second substrates, each of the second connection m

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kwon Heungkyu
• Lee Kang Joon
• Yoo Jaewook
• Lee Su-Chang

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title