Chip package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9698086-B2
Application number	US-201414306243-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Jul 5, 2012
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.

First claim

What is claimed is:

1. A chip package, comprising:
a leadframe comprising a die pad and a plurality of lead fingers; wherein the lead fingers extend out of the chip package;
at least a first chip comprising an active surface and a second surface opposite the active surface, the second surface of the first chip being attached to the die pad, the active surface of the at least first chip being bonded to a surface of one or more of the lead fingers via a first set of wire bonds, wherein the at least first chip includes a power MOS transistor;
a second chip bonded to one or more of the lead fingers;
a heat slug attached to the second chip; and
an encapsulation material encapsulating the die pad, the at least first chip, the second chip, and the first set of wire bonds;
wherein the die pad is exposed on a first surface of the chip package, configured to externally dissipate heat, and the heat slug is exposed on a second surface of the chip package opposite the first surface, configured to externally dissipate heat.

2. The chip package of claim 1 ,
wherein an active surface of the second chip faces the active surface of the at least first chip.

3. The chip package of claim 1 , further comprising:
a third chip attached on the first chip, the third chip being bonded to one or more of the lead fingers via a second set of wire bonds.

4. The chip package of claim 3 ,
wherein an active surface of the third chip faces the active surface of the second chip.

5. The chip package of claim 1 , further comprising:
a fourth chip attached on the die pad, the fourth chip being spaced from the first chip.

6. The chip package of claim 5 ,
wherein the fourth chip is bonded to one or more of the lead fingers via a third set of wire bonds.

7. The chip package of claim 5 , further comprising:
a clip having one end attached on the fourth chip and having the other end attached on one or more of the lead fingers.

8. A chip package, comprising:
a chip carrier comprising a chip contact structure and a chip attach structure;
wherein the chip contact structure extends out of the chip package;
an active surface of at least a first chip being bonded to a surface of the chip contact structure via wire bonds, and a second surface of the at least first chip opposite the active surface being attached to the chip attach structure;
a second chip bonded to the chip contact structure;
wherein an active surface of the second chip faces the active surface of the at least first chip;
a heat dissipation structure attached to the second chip; and
an encapsulation material encapsulating the chip attach structure, the at least first chip, the second chip, and the wire bonds;
wherein the chip attach structure is exposed on a first surface of the chip package, configured to externally dissipate heat at the first surface, and the heat dissipation structure is exposed on a second surface of the chip package opposite the first surface, configured to externally dissipate heat at the second surface.

9. A chip package, comprising:
a chip carrier comprising a chip contact structure and a chip attach structure;
wherein the chip contact structure extends out of the chip package;
an active surface of at least a first chip being bonded to a surface of the chip contact structure via a first chip bonding technology structure, and a second surface of the at least first chip opposite the active surface being attached to the chip attach structure;
a second chip being bonded to the chip contact structure via a second chip bonding technology structure, wherein the second chip bonding technology structure is different from the first chip bonding technology structure;
wherein an active surface of the second chip faces the active surface of the at least first chip;
a heat dissipation structure attached to the second chip; and
an encapsulation material encapsulating the chip attach structure, the at least first chip, the second chip, and the wire bonds;
wherein the chip attach structure is exposed on a first surface of the chip package, configured to externally dissipate heat, and the heat dissipation structure is exposed on a second surface of the chip package opposite the first surface, configured to externally dissipate heat.

10. The chip package of claim 9 , wherein
the first chip bonding technology structure comprises a plurality of bond wires; and
the second chip bonding technology structure comprises a flip chip structure.

11. The chip package of claim 1 ,
wherein a gap is disposed between the at least first chip and the second chip.

12. The chip package of claim 1 , further comprising
a clip having a first end and a second end; wherein the first end is attached to the first chip, the second chip, or both; and wherein the second end is attached on one or more lead fingers.

13. The chip package of claim 12 ,
wherein the clip has a hook shape.

14. The chip package of claim 11 ,
wherein the first set of wire bonds are disposed in the gap.

15. The chip package of claim 11 ,
wherein the gap is filled with the encapsulation material.

16. The chip package of claim 1 ,
wherein the encapsulation material at least partially encapsulates a top surface and a bottom surface of the plurality of lead fingers, wherein the top surface is opposite the bottom surface.

17. The chip package of claim 8 ,
wherein a gap is disposed between the at least first chip and the second chip.

18. The chip package of claim 17 ,
wherein the wire bonds are disposed in the gap.

19. The chip package of claim 9 ,
wherein a gap is disposed between the at least first chip and the second chip.

20. The chip package of claim 19 ,
wherein the first chip bonding technology structure is disposed in the gap.

Assignees

• Infineon Technologies Ag

Inventors

• Soller Tyrone Jon Donato

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title