Semiconductor chips having defect detecting circuits

Patent metadata

Field	Value
Publication number	US-9698066-B2
Application number	US-201615201675-A
Country	US
Kind code	B2
Filing date	Jul 5, 2016
Priority date	Oct 8, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a gate pattern on a substrate, the gate pattern being adjacent to an upper surface of the substrate, and the gate pattern being formed along an edge portion of a semiconductor chip region of the substrate;
a first wiring structure over the gate pattern, the first wiring structure being spaced apart from the gate pattern, and the first wiring structure including a first conductive pattern formed along the edge portion of the semiconductor chip region;
a first contact plug electrically connecting the gate pattern to a first portion of the first wiring structure;
a first defect detection circuit electrically connected to the gate pattern; and
a second defect detection circuit electrically connected to the first wiring structure.

2. The semiconductor chip of claim 1 , wherein
the gate pattern has a rectangular ring shape; and
ends of the gate pattern are adjacent to the first and second defect detection circuits and are spaced apart from one another, in a plan view.

3. The semiconductor chip of claim 1 , wherein
the first wiring structure further includes a first extension line and a second extension line;
the first conductive pattern has a rectangular ring shape;
ends of the first conductive pattern are adjacent to the first and second defect detection circuits, and are spaced apart from one another, in a plan view;
the first extension line contacts a sidewall of the first conductive pattern and extends toward the semiconductor chip region; and
the second extension line is spaced apart from the first extension line and contacts the first contact plug.

4. The semiconductor chip of claim 1 , wherein the first defect detection circuit comprises:
a clock signal circuit electrically connected to a first end portion of the gate pattern, the clock signal circuit configured to operate according to a gate clock signal;
a buffer circuit electrically connected to a second end portion of the gate pattern; and
an output circuit connected to the buffer circuit.

5. The semiconductor chip of claim 1 , wherein the second defect detection circuit comprises:
a clock signal circuit electrically connected to a first end portion of the first conductive pattern, the clock signal circuit configured to operate according to a first conductive pattern clock signal;
a buffer circuit electrically connected to a second end portion of the first conductive pattern; and
an output circuit connected to the buffer circuit.

6. The semiconductor chip of claim 1 , further comprising:
a second wiring structure over the first wiring structure, the second wiring structure being spaced apart from the first wiring structure, and the second wiring structure including a second conductive pattern formed along the edge portion of the semiconductor chip region;
a second contact plug electrically connected to the second wiring structure and a second portion of the first wiring structure; and
a third defect detection circuit electrically connected to the second wiring structure.

7. The semiconductor chip of claim 1 , further comprising:
a plurality of memory cells in a memory cell region of the substrate; wherein
the plurality of memory cells are between the substrate and the first wiring structure.

8. The semiconductor chip of claim 7 , wherein the plurality of memory cells include memory cells of a NAND flash memory device.

9. The semiconductor chip of claim 8 , wherein the NAND flash memory device is a three-dimensional memory device including a three-dimensional VNAND memory array.

10. A semiconductor chip, comprising:
a gate pattern on a substrate, the gate pattern being adjacent to an upper surface of the substrate, the gate pattern being formed along an edge portion of a semiconductor chip region of the substrate, and the gate pattern having a first end portion and a second end portion;
a first wiring structure over the gate pattern, the first wiring structure being spaced apart from the gate pattern, and the first wiring structure including a plurality of first conductive patterns overlapping the gate pattern;
a first contact plug electrically connecting the gate pattern to a portion of the first wiring structure;
a first defect detection circuit electrically connected to the first and second end portions of the gate pattern; and
a second defect detection circuit electrically connected to the plurality of first conductive patterns of the first wiring structure.

11. The semiconductor chip of claim 10 , wherein
the first wiring structure further includes a first extension line and a second extension line;
at least one of the plurality of first conductive patterns has a rectangular ring shape;
ends of the at least one first conductive pattern adjacent to the first and second defect detection circuits are spaced apart from one another, in a plan view;
the first extension line contacts a sidewall of the at least one first conductive pattern and extends toward the semiconductor chip region; and
the second extension line is spaced apart from the first extension line and contacts the first contact plug.

12. The semiconductor chip of claim 10 , wherein
the first extension line is connected to the second defect detection circuit; and
the second extension line is connected to the first defect detection circuit.

13. The semiconductor chip of claim 10 , wherein the first and second defect detection circuits are in the semiconductor chip region.

14. The semiconductor chip of claim 10 , wherein the first defect detection circuit comprises:
a clock signal circuit electrically connected to the first end portion of the gate pattern, the clock signal circuit configured to operating according to a gate clock signal;
a buffer circuit electrically connected to the second end portion of the gate pattern; and
an output circuit connected to the buffer circuit.

15. The semiconductor chip of claim 10 , wherein the second defect detection circuit comprises:
a clock signal circuit electrically connected to a first end portion of at least one of the plurality of first conductive patterns, the clock signal circuit configured to operate according to a conductive pattern clock signal;
a buffer circuit electrically connected to a second end portion of the at least one first conductive pattern; and
an output circuit connected to the buffer circuit.

16. A semiconductor chip comprising:
a gate pattern on a substrate;
an interlayer insulation layer on the gate pattern;
a first wiring structure on the interlayer insulation layer, the first wiring structure electrically connected to the gate pattern via a contact plug through the interlayer insulation layer; and
a defect detection circuit electrically connected to the gate pattern and the first wiring structure, the defect detection circuit configured to separately detect (i) at least one first defect in the first wiring structure and (ii) at least one second defect in at least one of the gate pattern and the substrate.

17. The semiconductor chip of claim 16 , wherein
the at least one second defect includes at least one crack in the at least one of the gate pattern and the substrate; and
the defect detection circuit includes a first crack detection circuit electrically connected to the gate pattern, the first crack detection circuit configured to detect the at least one crack in the at least one of the gate pattern and the substrate.

18. The semiconductor chip of claim 17 , wherein
the at least one first defect includes at least one crack in the first wirin

Assignees

• Lee Bo-Ra
• Jeong Jae-Ho
• Baek Nam-Gyu
• WOO Hyo-Seok
• Yoon Hyun-Sook
• Lee Kwang-Yong
• Samsung Electronics Co Ltd

Inventors

• Lee Bo-Ra
• Jeong Jae-Ho
• Baek Nam-Gyu
• WOO Hyo-Seok
• Yoon Hyun-Sook
• Lee Kwang-Yong

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H01L22/32 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L23/562

  Electricity · mapped topic