Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-9698059-B2
Application number	US-201514686787-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Mar 19, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a dielectric layer on the substrate, wherein the dielectric layer comprises a first gate trench, a second gate trench and a third gate trench formed therein;
performing a first threshold voltage implantation process in the first gate trench;
performing a third threshold voltage implantation process in the third gate trench;
after performing the third threshold voltage implantation process, forming a first work function layer in the first gate trench after the first threshold voltage implantation process;
forming a second work function layer in the second gate trench, and on the first work function layer in the first gate trench, wherein the first work function layer and the second work function layer have a same conductive type; and
forming a third work function layer in the third gate trench, and on the second work function layer formed in the second gate trench and the first gate trench, wherein the third work function layer has a different conductive type from that of the first work function layer.

2. The method of forming a semiconductor device according to claim 1 , further comprising:
performing a second threshold voltage implantation process in the second gate trench before forming the first work function layer, wherein the second threshold voltage implantation process is performed by implanting different dopants from that of the first threshold voltage implantation process.

3. The method of forming a semiconductor device according to claim 1 , further comprising:
forming a first dummy gate structure and a second dummy gate structure on the substrate, wherein each of the first dummy gate structure and the second dummy gate structure comprises a dummy gate electrode and an interfacial layer;
removing the dummy gate electrode of the first dummy gate structure to form the first gate trench; and
removing the dummy gate electrode of the second dummy gate structure to form the second gate trench.

4. The method of forming a semiconductor device according to claim 3 , further comprising:
removing the interfacial layer of the first dummy gate structure before the first threshold voltage implantation process is performed.

5. The method of forming a semiconductor device according to claim 3 , further comprising:
removing the interfacial layer of the first dummy gate structure after the first threshold voltage implantation process is performed.

6. The method of forming a semiconductor device according to claim 3 , further comprising:
forming a fin shaped structure on the substrate, wherein the first dummy gate structure and the second dummy gate structure are formed on the fin shaped structure.

7. The method of forming a semiconductor device according to claim 1 , wherein the first work function layer and the second work function layer comprise different materials or have different thicknesses.

8. A method of forming a semiconductor device, comprising:
providing a substrate;
performing a first threshold voltage implantation process on the entire substrate;
forming a first dummy gate structure and a second dummy gate structure on the substrate, wherein each of the first dummy gate structure and the second dummy gate structure has an interfacial layer and a dummy gate electrode;
removing the dummy gate electrode of the first dummy gate structure to form a first gate trench; and
performing a second threshold voltage implantation process in the first gate trench right after removing the dummy gate electrode of the first dummy gate structure.

9. The method of forming a semiconductor device according to claim 8 , wherein the second threshold voltage implantation process is performed by implanting different dopants from that of the first threshold voltage implantation process.

10. The method of forming a semiconductor device according to claim 8 , further comprising:
removing the dummy gate electrode of the second dummy gate structure to form a second gate trench; and
performing a third threshold voltage implantation process in the second gate trench right after removing the dummy gate electrode of the second dummy gate structure, wherein the third threshold voltage implantation process is performed by implanting different dopants from that of the first threshold voltage implantation process.

11. The method of forming a semiconductor device according to claim 8 , further comprising:
removing the interfacial layer of the first dummy gate structure before the second threshold voltage implantation process is performed.

12. The method of forming a semiconductor device according to claim 8 , further comprising:
removing the interfacial layer of the first dummy gate structure after the second threshold voltage implantation process is performed.

13. The method of forming a semiconductor device according to claim 8 , further comprising:
forming a fin shaped structure on the substrate, wherein the first dummy gate structure and the second dummy gate structure are formed on the fin shaped structure.

Assignees

• United Microelectronics Corp

Inventors

• Gan Tian Choy
• Hsiao Chu-Yun
• Hsu Chia-Fu

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L21/26513

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic