Optical interconnect in high-speed memory systems

Patent metadata

Field	Value
Publication number	US-9697883-B2
Application number	US-201615052161-A
Country	US
Kind code	B2
Filing date	Feb 24, 2016
Priority date	Aug 30, 2001
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.

First claim

We claim:

1. A computer system, comprising:
a processor; and
a memory system connected to said processor, said memory system comprising:
a memory controller;
at least one memory device;
an optical path connected between said memory controller and said at least one memory device for optically passing data between said controller and said at least one memory device;
a first electro-optical converter configured to convert an electrical signal output from said controller to an optical signal for transmission on said optical path; and
a second electro-optical converter configured to convert an optical signal on said optical path to an electrical signal and to transmit said electrical signal to said controller,
wherein said controller and at least one memory device are integrated on the same die.

2. A computer system of claim 1 , wherein said controller is configured to transmit data to said at least one memory device through said optical path.

3. A computer system of claim 1 , wherein said controller is configured to receive data from said at least one memory device through said optical path.

4. A computer system of claim 1 , wherein said optical path comprises a plurality of multiplexed optical channels, said data being transmitted over said multiplexed optical channels.

5. A computer system of claim 1 , wherein said first electro-optical converter is wavelength-adjustable.

6. A computer system of claim 5 , further comprising a wavelength-sensing mechanism connected to said controller, the wavelength-sensing mechanism configured to provide wavelength information to said controller with respect to an optical signal on said optical path.

7. A computer system of claim 1 , further comprising:
a multiplexer associated with said controller and configured to multiplex said optical channels, and
a demultiplexer associated with said at least one memory device and configured to demultiplex said multiplexed optical channels.

8. A computer system of claim 1 , comprising:
a multiplexer associated with said at least one memory device and configured to multiplex optical channels and providing multiplexed optical channels to said optical path; and
a demultiplexer associated with said memory controller and configured to demultiplex said multiplexed optical channels.

9. A computer system of claim 1 , comprising an optical multiplexer and demultiplexer located on each side of said optical path.

10. A computer system of claim 1 , wherein said at least one memory device is located on a memory module.

11. The computer system of claim 10 , wherein said memory module comprises an electro-optical converter configured to connect optical data from said optical path to electrical signals for said at least one memory device.

12. A computer system of claim 11 , wherein said wavelength sensing mechanism is located at a controller side of said optical path.

13. A computer system of claim 12 , wherein said controller is configured to provide wavelength adjustment information to said converter.

14. The computer system of claim 1 , wherein said processor, controller, at least one memory device and optical path are all integrated on the same die.

15. The computer system of claim 1 , wherein said processor and at least one memory device are provided on separate dies.

16. The computer system of claim 15 , wherein said separate dies are provided in a common package.

17. A method of operating a memory system, the method comprising:
receiving, at a first electro-optical converter, an electrical signal from at least one memory device;
converting, via the first electro-optical converter, said received electrical signal into an optical signal;
transmitting said optical signal over an optical path to a second electro-optical converter;
converting, via the second electro-optical converter, said received optical signal into an electrical signal; and
transmitting said electrical signal to a memory controller,
wherein said memory device, memory controller, first electro-optical converter, and second electro-optical converter are all on integrated the same die.

18. The method of claim 17 , wherein said optical path comprises a plurality of multiplexed optical channels, said optical signal being transmitted over said multiplexed optical channels.

19. The method of claim 18 , further comprising:
multiplexing optical channels and providing multiplexed optical channels to said optical path; and
demultiplexing said multiplexed optical channels.

20. The method of claim 18 , wherein the memory system comprises an optical multiplexer and demultiplexer located on each side of said optical path.

21. The method of claim 18 , wherein converting, via the first electro-optical converter, said received electrical signal into the optical signal comprises adjusting the wavelength of said optical path.

22. The method of claim 18 , further comprising multiplexing said optical channels, and demultiplexing said multiplexed optical channels.

23. The method of claim 17 , wherein said at least one memory device is located on a memory module.

24. The method of claim 17 , further comprising providing wavelength information to said controller with respect to an optical signal on said optical path.

25. The method of claim 24 , wherein said controller provides wavelength adjustment information to said first electro-optical converter.

26. The method of claim 17 , further comprising integrating a processor for communicating with said at least one memory device within the same die.

Assignees

• Micron Technology Inc

Inventors

• Baker Jacob
• Keeth Brent

Classifications

• H04L12/40013

  Details regarding a bus controller · CPC title

• H04Q11/0071

  Provisions for the electrical-optical layer interface · CPC title

• G06F13/4234

  being a memory bus · CPC title

• H04B10/802

  for isolation, e.g. using optocouplers · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic