Word line divider and storage device

Patent metadata

Field	Value
Publication number	US-9697878-B2
Application number	US-201213472789-A
Country	US
Kind code	B2
Filing date	May 16, 2012
Priority date	May 20, 2011
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A word line divider which has a simplified circuit structure and can operate stably is provided. A storage device which has a simplified circuit structure and can operate stably is provided. A transistor whose leakage current is extremely low is connected in series with a portion between a word line and a sub word line so that the word line divider is constituted. The transistor can include an oxide semiconductor for a semiconductor layer in which a channel is formed. Such a word line divider whose circuit structure is simplified is used in the storage device.

First claim

What is claimed is:

1. A storage device comprising:
a word line;
a first sub word line;
a second sub word line;
a first transistor; a second transistor;
a first selection transistor;
a second selection transistor;
a first capacitor; and
a second capacitor,
wherein a gate of the first selection transistor is electrically connected to the first sub word line,
wherein a gate of the second selection transistor is electrically connected to the second sub word line,
wherein the first capacitor is electrically connected to one of a source and a drain of the first selection transistor,
wherein the second capacitor is electrically connected to one of a source and a drain of the second selection transistor,
wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the word line,
wherein the other of the source and the drain of the first transistor is electrically connected to the first sub word line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second sub word line,
wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×10 −17 A or lower,
wherein the first transistor, the first selection transistor and the first capacitor overlap each other, and
wherein the second transistor, the second selection transistor and the second capacitor overlap each other.

2. The storage device according to claim 1 , wherein each of the first transistor and the second transistor comprises a channel, and the channel comprises an oxide semiconductor.

3. The storage device according to claim 1 , comprising:
a first memory cell comprising the first selection transistor and the first capacitor; and
a second memory cell comprising the second selection transistor and the second capacitor.

4. The storage device according to claim 3 , wherein each of the first memory cell and the second memory cell is a DRAM.

5. The storage device according to claim 1 ,
wherein each of the first selection transistor and the second selection transistor comprises a channel comprising an oxide semiconductor.

6. The storage device according to claim 1 , further comprising a third transistor and a fourth transistor,
wherein the one of the source and the drain of the first selection transistor is electrically connected to a gate of the third transistor and the first capacitor, and
wherein the one of the source and the drain of the second selection transistor is electrically connected to a gate of the fourth transistor and the second capacitor.

7. The storage device according to claim 1 ,
wherein each of the first selection transistor and the second selection transistor comprises a channel comprising silicon.

8. A storage device comprising:
a first bit line;
a second bit line;
a word line;
a first sub word line;
a second sub word line;
a first transistor;
a second transistor;
a first memory cell comprising a first selection transistor and a first data retention portion comprising a first capacitor; and
a second memory cell comprising a second selection transistor and a second data retention portion comprising a second capacitor,
wherein one of a source and a drain of the first selection transistor is electrically connected to the first bit line,
wherein one of a source and a drain of the second selection transistor is electrically connected to the second bit line,
wherein the other of the source and the drain of the first selection transistor is electrically connected to the first data retention portion,
wherein the other of the source and the drain of the second selection transistor is electrically connected to the second data retention portion,
wherein a gate of the first selection transistor is electrically connected to the first sub word line,
wherein a gate of the second selection transistor is electrically connected to the second sub word line,
wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the word line,
wherein the other of the source and the drain of the first transistor is electrically connected to the first sub word line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second sub word line,
wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×10 −17 A or lower,
wherein the first transistor, the first selection transistor and the first capacitor overlap each other, and
wherein the second transistor, the second selection transistor and the second capacitor overlap each other.

9. The storage device according to claim 8 , wherein each of the first memory cell and the second memory cell is a DRAM.

10. The storage device according to claim 8 , wherein off-state leakage current per micrometer of channel width of each of the first selection transistor and the second selection transistor is 1×10 −17 A or lower.

11. The storage device according to claim 8 , wherein each of the first selection transistor and the second selection transistor comprises a channel, and the channel comprises an oxide semiconductor.

12. The storage device according to claim 8 ,
wherein the first capacitor is electrically connected to the other of the source and the drain of the first selection transistor,
wherein the second capacitor is electrically connected to the other of the source and the drain of the second selection transistor, and
wherein the first selection transistor and the second selection transistor comprising a channel comprising an oxide semiconductor.

13. The storage device according to claim 8 ,
wherein the first data retention portion comprises a third transistor,
wherein the second data retention portion comprises a fourth transistor,
wherein a gate of the third transistor and the first capacitor are electrically connected to the other of the source and the drain of the first selection transistor,
wherein a gate of the fourth transistor and the second capacitor are electrically connected to the other of the source and the drain of the second selection transistor, and
wherein the first selection transistor and the second selection transistor comprising a channel comprising an oxide semiconductor.

14. The storage device according to claim 8 , wherein each of the first transistor and the second transistor comprises a channel, and the channel comprises an oxide semiconductor.

15. The storage device according to claim 8 , wherein each of the first selection transistor and the second selection transistor comprises a channel, and the channel comprises silicon.

16. A storage device comprising:
a word line;
a first sub word line;
a second sub word line;
a first transistor;
a second transistor;
a first selection transistor;
a second selection transistor;
a first capacitor; and
a second capacitor,
wherein a gate of the first selection transistor is electrically connected to the first sub word line,
wherein a gate of the second selection transistor is electrically connected to the second sub word line,
wherein the first capacitor is electrically connected to one of a source and a drain of the first selection transistor,
wherein the second capacitor is electrically connected to one of a source and a drain of the second selection transistor,
wherein one of a source and a drain of the first transistor and one of a source and

Assignees

• Nagatsuka Shuhei
• Matsuzaki Takanori
• Inoue Hiroki
• Semiconductor Energy Lab

Inventors

• Nagatsuka Shuhei
• Matsuzaki Takanori
• Inoue Hiroki

Classifications

• G11C2216/14

  Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C8/14 Primary

  Word line organisation; Word line lay-out · CPC title