Vertical bit vector shift in memory

Patent metadata

Field	Value
Publication number	US-9697876-B1
Application number	US-201615057736-A
Country	US
Kind code	B1
Filing date	Mar 1, 2016
Priority date	Mar 1, 2016
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.

First claim

What is claimed is:

1. A method for shifting data, comprising:
storing a vertical bit vector of data in a memory array, wherein:
the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines; and
the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and

performing, using sensing circuitry, a vertical bit vector shift of elements of the vertical bit vector by performing a first AND operation with an element of a vertical shift bit vector and an element of the vertical bit vector that is being shifted.

2. The method of claim 1 , wherein the performing the vertical bit vector shift is performed in the memory array.

3. The method of claim 2 , wherein the at least one of the AND, OR, invert, and shift operations are performed using sensing circuitry coupled to each on a number of columns of complementary sense lines.

4. The method of claim 1 , wherein performing the vertical bit vector shift includes performing at least one of an AND, an OR, an invert, and a shift operations, wherein the at least one of the AND, OR, invert, and shift operations is based on elements in a vertical shift bit vector.

5. The method of claim 1 , wherein the performing the vertical bit vector shift includes shifting the elements of the vertical bit vector by a particular value indicated by the vertical shift bit vector.

6. The method of claim 5 , wherein the particular value includes a shift value of 2 n-1 for each element of the vertical shift bit vector and wherein n corresponds to an element's position in the vertical shift bit vector.

7. The method of claim 5 , wherein the vertical shift bit vector is stored in memory cells coupled to the sense line that is coupled to the memory cells storing the bit vector.

8. The method of claim 5 , wherein performing the vertical bit vector shift includes performing shift operations, wherein each shift operation is performed on each element of the vertical bit vector for each element of the vertical shift bit vector.

9. The method of claim 1 , wherein performing the vertical bit vector shift includes shifting elements of the vertical bit vector toward the most significant bit.

10. The method of claim 1 , wherein performing the vertical bit vector shift includes shifting elements of the vertical bit vector toward the least significant bit.

11. The method of claim 1 , wherein the method includes storing a result of the vertical bit vector shift in memory cells coupled to a plurality of access lines of the memory array that are different than the plurality of access lines coupled to the memory cells that stored the vertical bit vector.

12. The method of claim 1 , wherein the method includes storing a result of the vertical bit vector shift in memory cells coupled to the sense line that is coupled to the memory cells storing the vertical bit vector.

13. A method for shifting data, comprising:
storing bit vectors of data in a memory array, wherein:
each bit vector is stored in memory cells coupled to a sense line and a plurality of access lines; and
each bit vector is separated by at least one sense line from a neighboring bit vector; and

shifting elements of the bit vectors by:
performing shift operations, wherein each of the shift operations shift elements of the bit vectors of data by a number of positions indicated by a vertical shift bit vector and wherein elements of each of the vertical shift bit vectors coupled to common access lines include at least one of values 1 and 0 and wherein a value of 1 indicates that corresponding bit vectors are shifted and a value of 0 indicates that corresponding bit vectors are not shifted or a value of 0 indicates that corresponding bit vectors are shifted and a value of 1 indicates that corresponding bit vectors are not shifted.

14. The method claim 13 , wherein the vertical shift bit vector is stored in memory cells that are coupled the sense line that is coupled to memory cells storing a corresponding one of the bit vectors.

15. The method of claim 13 , wherein performing the shift operations includes shifting elements of each of the number of bit vectors that are coupled to a common access line by an amount indicated by the vertical shift bit vector.

16. The method of claim 13 , wherein performing the shift operations includes performing a shift iteration on each element of each of the bit vectors that are coupled to a common access line by an amount indicated by elements of the vertical shift bit vector.

17. The method claim 16 , wherein performing the shift iteration includes inverting an element of the vertical shift bit vector, performing an AND operation with the inverted element of the vertical shift bit vector and an element of the bit vectors, and storing the result of the AND operation in destination memory cells corresponding to the element of the bit vectors.

18. The method of claim 16 , wherein performing the shift iteration includes performing a first AND operation with a first element of the vertical shift bit vector and a first element of the bit vectors that is being shifted, inverting the first element of the vertical shift bit vector, performing a second AND operation with the inverted element of the vertical bit vector operands and the first element of the bit corresponding to a shifted bit vector, performing an OR operation on the result of the first AND operation and the second AND operation, and storing a result of the OR operation in destination memory cells.

19. The method of claim 13 , wherein performing the number of shift operations includes shifting an element of the elements by 2 n-1 positions as indicated by elements of each of the vertical bit vector operands that are coupled to a common access line and wherein n corresponds to an element's position in the vertical shift bit vector.

20. The method of claim 13 , wherein the method includes storing a bit vector of each of the shift operations in memory cells coupled an access line that is different than the plurality of access lines coupled to the memory cells storing the bit vectors.

21. An apparatus comprising:
a first group of memory cells coupled to a sense line and a first plurality of access lines and configured to store a number of elements of a vertical bit vector; and
a controller configured to cause:
shifting of the number of elements of the vertical bit vector by a number of positions indicated by a vertical shift bit vector, wherein elements of the vertical shift bit vector include at least one of values 1 and 0 and wherein a value of 1 indicates that corresponding bit vectors are shifted and a value of 0 indicates that corresponding bit vectors are not shifted or a value of 0 indicates that corresponding bit vectors are shifted and a value of 1 indicates that corresponding bit vectors are not shifted.

22. The apparatus of claim 21 , wherein the vertical shift bit vector is stored in a second group of memory cells coupled to the sense line and a second plurality of access lines.

23. The apparatus of claim 21 , wherein the sensing circuitry is configured to store a shifted vertical bit vector in a third group of memory cells coupled to the sense line and a third plurality of access lines.

24. The apparatus of claim 21 , wherein the vertical shift bit vector includes a number of elements and each element of the vertical shift bit vector corresponds to an amount to shift the number of elements of the

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay
• Wheeler Kyle B

Classifications

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title