System and method for designing cell rows

Patent metadata

Field	Value
Publication number	US-9697319-B2
Application number	US-201514679843-A
Country	US
Kind code	B2
Filing date	Apr 6, 2015
Priority date	May 14, 2009
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
placing a first plurality of cells into a first cell row with a first cell row height;
placing a second plurality of cells into a second cell row with a second cell row height;
placing a first cell into both the first cell row and the second cell row, wherein the first cell has a first cell height that is greater than the first cell row height and the second cell row height and less than a sum of the first cell row height and the second cell row height;
adding a first filler region extending from the first cell to an edge of the first cell row, the first filler region connecting the first cell to a second cell adjacent to the first cell, the first filler region comprising a well with a stair step shape; and
manufacturing a semiconductor device with the first filler region.

2. The method of claim 1 , wherein the placing the first plurality of cells further comprises receiving the first plurality of cells from a cell library.

3. The method of claim 2 , wherein the adding the first filler region further comprises obtaining the first filler region from the cell library.

4. The method of claim 2 , wherein the adding the first filler region further comprises obtaining the first filler region from outside of the cell library.

5. The method of claim 1 , further comprising adding a second filler region on an opposite side of the first cell than the first filler region, the second filler region connecting the first cell to a third cell adjacent to the first cell.

6. The method of claim 5 , further comprising adding a third filler region extending from the first filler region to the second filler region.

7. The method of claim 6 , further comprising adding a fourth filler region extending from the first filler region to the second filler region on an opposite side of the first cell than the third filler region.

8. The method of claim 6 , wherein the third filler region has a dimension that is equal to a sum of the first cell height and the second cell height.

9. A method for manufacturing a semiconductor device, the method comprising:
placing a plurality of cells into a first cell row with a first cell row height, wherein a first cell of the plurality of cells has a first cell height different from the first cell row height and different from an integer multiple of the first cell row height, wherein the first cell comprises an implant region of a first conductivity type across one edge of the first cell, the implant region being adjacent to a well region having a different conductivity type;
placing a first extension region extending in a first direction away from the first cell, the first direction being perpendicular with an edge of the first cell row, the first extension region comprising a first implant extension having the first conductivity type and being adjacent to the implant region;
placing a second extension region extending in a second direction away from the first cell, the second direction being parallel with the edge of the first cell row, wherein the first extension region and the second extension region electrically connect the first cell to adjacent cells, the second extension region comprising a second implant extension having the first conductivity type and being adjacent to the implant region and the first implant extension, wherein the first cell, the first extension region and the second extension region are part of an integrated circuit design; and
sending the integrated circuit design to a semiconductor manufacturing tool.

10. The method of claim 9 , wherein the placing the plurality of cells further comprises receiving the plurality of cells from one or more cell libraries.

11. The method of claim 10 , wherein each one of the one or more cell libraries stores cell having similar cell heights.

12. The method of claim 10 , wherein the one or more cell libraries is one cell library.

13. The method of claim 10 , wherein the placing the first extension region further comprises obtaining the first extension region from the one or more cell libraries.

14. The method of claim 10 , wherein the placing the first extension region further comprises obtaining the first extension region from outside of the one or more cell libraries.

15. A method of manufacturing a semiconductor device, the method comprising:
placing a first plurality of cells into a first cell row with a first cell row height;
placing a second plurality of cells into a second cell row with a second cell row height;
placing a first cell into both the first cell row and the second cell row, wherein the first cell has a first cell height that is greater than the first cell row height and the second cell row height and less than a sum of the first cell row height and the second cell row height;
adding a first filler region extending from the first cell to an edge of the first cell row, the first filler region connecting the first cell to a second cell adjacent to the first cell, the first filler region comprising a well with a stair step shape and a first implant extension being adjacent to the well; and
manufacturing a semiconductor device with the first filler region.

16. The method of claim 15 , wherein the placing a first plurality of cells into the first cell row comprises:
receiving the first plurality of cells from a cell library; and
incorporating the first plurality of cells into the first cell row.

17. The method of claim 16 , wherein the adding the first filler region comprises:
receiving the first filler region from the cell library; and
incorporating the first filler region with the first plurality of cells.

18. The method of claim 16 , wherein the cell library stores cells of a similar size.

19. The method of claim 16 , wherein the cell library is a single cell library.

20. The method of claim 16 , wherein the adding the first filler region comprises:
receiving the first filler region from outside of the cell library; and
incorporating the first filler region with the first plurality of cells.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yun-Han
• Kuo Wu-An

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5072 Primary

  Physics · mapped topic