Concurrent virtual storage management

Patent metadata

Field	Value
Publication number	US-9697143-B2
Application number	US-201514871265-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A memory system is configured for access by a plurality of computer processing units. An address lock bit is configured in a translation table of the memory system. The address lock supports both address lock shared and address lock exclusive functions. A storage manager of an operating system configured to obtain exclusive access to an entry in a DAT table either by obtaining an address space lock exclusive or obtaining an address space lock shared, and setting a lock bit in a DAT entry.

First claim

What is claimed is:

1. A system, comprising:
a memory system configured for access by a plurality of computer processing units;
a lock bit configured in a translation table of the memory system, the lock bit supporting both address lock shared and address lock exclusive functions;
a backing bit and an invalid bit configured in a segment table entry of the memory system; and
a storage manager of an operating system, the storage manager configured to obtain exclusive access to an entry in a dynamic address translation (DAT) table either by obtaining an address space lock exclusive or obtaining an address space lock shared, and setting the lock bit in a DAT entry,
wherein when a lock is held on a segment corresponding to the segment table entry, a location field of the segment table entry is based at least in part on respective values of the backing bit and the invalid bit such that:
when the invalid bit is 0 and the backing bit is 0, the location field of the segment table entry holds a real address of a page table frame;
when the invalid bit is 0 and the backing bit is 1, the location field of the segment table entry holds a real address of 1 MB frame; and
when the invalid bit is 1 and the backing bit is 1, the location field of the segment table entry holds a real address of 1 MB page in an auxiliary storage location.

2. The system of claim 1 , wherein the DAT table is a segment table and the lock bit is set in the segment table entry of the segment table.

3. The system of claim 1 , wherein the DAT table is a page table and the lock bit is set in a corresponding page table entry of the page table.

4. The system of claim 1 , wherein upon determining that a page subject to the address space lock shared is already locked, the address space lock shared is dropped, and the address space lock exclusive is obtained prior to performing a corresponding task by a computer processing unit.

5. The system of claim 4 , wherein the address space lock exclusive is released subsequent to performing the corresponding task by the computer processing unit.

6. The system of claim 1 , wherein upon determining that a page subject to the address space lock shared is not locked via the lock bit, the page is locked by the storage manager, a corresponding task is performed by a computer processing unit, the page is unlocked, and the address space lock shared is released.

7. The system of claim 1 , wherein the tasks include at least one of a page fault operation, a page fix operation, a page unfix operation, a segment fault, and a page steal operation.

8. The system of claim 1 , wherein when the address space lock is held shared, a storage management function serializes, via a serialization instruction, a lowest valid level in the DAT table mapping a virtual address by setting a corresponding one of the lock bits in a segment table entry and a page table entry.

9. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform:
obtaining, via a storage manager of an operating system for a memory system configured for access by a plurality of computer processing units, exclusive access to an entry in a DAT table either by obtaining an address space lock exclusive or obtaining an address space lock shared, wherein a lock bit is configured in the table and supports both address lock shared and address lock exclusive functions; and
locking a segment, wherein a backing bit and an invalid bit are configured in a segment table entry of the memory system, and wherein when a lock is held on a segment corresponding to the segment table entry, a location field of the segment table entry is based at least in part on respective values of the backing bit and the invalid bit such that:
when the invalid bit is 0 and the backing bit is 0, the location field of the segment table entry holds a real address of a page table frame;
when the invalid bit is 0 and the backing bit is 1, the location field of the segment table entry holds a real address of 1 MB frame; and
when the invalid bit is 1 and the backing bit is 1, the location field of the segment table entry holds a real address of 1 MB page in an auxiliary storage location.

10. The computer program product of claim 9 , wherein upon determining that a page subject to lock shared is already locked, the address space lock shared is dropped, and the address lock exclusive is obtained prior to performing a corresponding task by a computer processing unit; wherein the address space lock exclusive is released subsequent to performing the corresponding task by the computer processing unit.

Assignees

• IBM

Inventors

• Mari Charles E
• Morgenstern Harris M
• Rankin Thomas F
• Relson Peter J
• Tzortzatos Elpida

Classifications

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/084

  with a shared cache · CPC title