Method of managing dynamic memory reallocation and device performing the method

Patent metadata

Field	Value
Publication number	US-9697111-B2
Application number	US-201313957968-A
Country	US
Kind code	B2
Filing date	Aug 2, 2013
Priority date	Aug 2, 2012
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A method of managing dynamic memory reallocation includes receiving an input address including a block bit part, a tag part, and an index part and communicating the index part to a tag memory array, receiving a tag group communicated by the tag memory array based on the index part, analyzing the tag group based on the block bit part and the tag part and changing the block bit part and the tag part based on a result of the analysis, and outputting an output address including a changed block bit part, a changed tag part, and the index part.

First claim

What is claimed is:

1. A system comprising:
a system on chip (SoC) including a memory remapper, a first memory controller, a second memory controller and a processor configured to control the memory remapper;
a first memory; and
a second memory stacked on the SoC, and configured to operate faster than the first memory, the second memory being a wide input/output (I/O) mobile dynamic random access memory (DRAM),
wherein the first memory controller receives first access control signals from the memory remapper, and controls an access operation with respect to the first memory based on the first access control signals,
wherein the second memory controller receives second access control signals from the memory remapper, and controls an access operation with respect to the second memory based on the second access control signals,
wherein the memory remapper performs a memory operation between the first memory and the second memory, by moving first data stored in the first memory to the second memory, by moving second data stored in the second memory to the first memory, and/or by swapping the first data and the second data, and
wherein the memory remapper includes:
a tag memory array configured to store a plurality of tag groups, each of the plurality of tag groups updating information used to change an input address into a corresponding output address;
an address translator configured to receive the input address and to generate a relocation command including the input address and the corresponding output address necessary for data swapping; and
a relocator configured to control the data swapping between the first memory and the second memory in response to the relocation command.

2. The system of claim 1 , wherein data that is frequently accessed is stored in the second memory.

3. The system of claim 1 , wherein the memory remapper manages a data copying operation between the first memory and the second memory.

4. The system of claim 1 , wherein the first memory is a dynamic random access memory (DRAM).

5. The system of claim 1 , wherein the first memory is a main memory and the second memory is a cache memory.

6. The system of claim 1 , wherein the memory remapper outputs to the first memory controller and/or the second memory controller an address for the memory operation.

7. The system of claim 1 , wherein capacity and power consumption of the second memory is less than those of the first memory.

8. The system of claim 1 , wherein the processor is a multi-core processor that includes at least two processor cores.

9. The system of claim 8 , wherein each of the at least two processor cores communicates with the memory remapper.

10. The system of claim 8 , wherein the memory remapper performs the memory operation based on a command that is outputted from one of the at least two processor cores.

11. A system comprising:
a system on chip (SoC) including a memory remapper, a first memory controller, a second memory controller and a processor configured to control the memory remapper;
a first memory; and
a second memory stacked on the SoC and configured to operate faster than the first memory, the second memory being a wide input/output (I/O) mobile dynamic random access memory (DRAM),
wherein the first memory controller receives first access control signals from the memory remapper, and controls an access operation with respect to the first memory based on the first access control signals,
wherein the second memory controller receives second access control signals from the memory remapper, and controls an access operation with respect to the second memory based on the second access control signals,
wherein the memory remapper controls operations for first data stored in the first memory and for second data stored in the second memory,
wherein the memory remapper outputs to the first memory controller and/or the second memory controller an address for data reallocation, and
wherein the memory remapper includes:
a tag memory array configured to store a plurality of tag groups, each of the plurality of tag groups updating information used to change an input address into a corresponding output address;
an address translator configured to receive the input address and to generate a relocation command including the input address and the corresponding output address necessary for data swapping; and
a relocator configured to control the data swapping between the first memory and the second memory in response to the relocation command.

12. The system of claim 11 , wherein the first memory is a DRAM.

13. The system of claim 11 , wherein the memory remapper controls data swapping between the first memory and the second memory or data moving between the first memory and the second memory.

14. The system of claim 11 , wherein the processor is a multi-core processor that includes at least two processor cores.

15. The system of claim 11 , wherein the processor includes:
a first processor core:
a second processor core:
a first cache controller configured to communicate with the first processor core; and
a second cache controller configured to communicate with the second processor core.

16. A system comprising:
a system on chip (SoC) including a memory remapper, a first memory controller, a second memory controller and a multi-core processor configured to control the memory remapper;
a first memory having first memory regions; and
a second memory stacked on the SoC and having second memory regions, the second memory being configured to operate faster than the first memory and to store data that is frequently accessed,
wherein the first memory controller receives first access control signals from the memory remapper, and controls an access operation with respect to the first memory based on the first access control signals,
wherein the second memory controller receives second access control signals from the memory remapper, and controls an access operation with respect to the second memory based on the second access control signals,
wherein the memory remapper manages addresses corresponding to a sum of the first memory regions and the second memory regions,
wherein the first memory and the second memory are heterogeneous memories to each other, and
wherein the memory remapper includes:
a tag memory array configured to store a plurality of tag groups, each of the plurality of tag groups updating information used to change an input address into a corresponding output address;
an address translator configured to receive the input address and to generate a relocation command including the input address and the corresponding output address necessary for data swapping; and
a relocator configured to control the data swapping between the first memory and the second memory in response to the relocation command.

17. The system of claim 16 , wherein the memory remapper controls data swapping that is performed on first data stored in the first memory and second data stored in the second memory.

18. The system of claim 16 , wherein the memory remapper manages addresses for the first memory regions of the first memory and addresses for the second memory regions of the second memory, and controls operations for first data stored in the first memory regions and for second data stored in the second memory regions.

19. The system of claim 16 , wherein the first memory is a dynamic random access memory (DRAM), and the second memory is a wide input/output (I/O) DRAM.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Jun Hee
• Lee Sung Hyun
• Kang Dong Soo

Classifications

• G06F12/023 Primary

  Free address space management · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title