Very-long instruction word (VLIW) processor and compiler for executing instructions in parallel

Patent metadata

Field	Value
Publication number	US-9697004-B2
Application number	US-201414247735-A
Country	US
Kind code	B2
Filing date	Apr 8, 2014
Priority date	Feb 12, 2004
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src 1 , src 2 , and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

First claim

The invention claimed is:

1. A very long instruction word (VLIW) processor which performs a plurality of operations in parallel, the VLIW processor comprising:
an instruction register for holding a very long instruction word; and
a plurality of operation units,
wherein the very long instruction word is composed of a plurality of first fields each designating an operation to be performed, and a second field partitioned into a plurality of sub-fields,
the second field is operable to be referred to by at least two of the first fields at once,
each of the sub-fields in the second field is operable to be correlated with any one of the first fields, and
multiple operations defined by the plurality of first fields and the second field are performed in parallel by the plurality of operation units.

2. The VLIW processor according to claim 1 , further comprising:
an instruction decoder for decoding the very long instruction word held in the instruction register,
wherein the instruction decoder is operable to decode a first one of the first fields, a second one of the first fields and a third one of the first fields in parallel.

3. The VLIW processor according to claim 2 ,
wherein, when the instruction decoder decodes a first very long instruction word, the first one of the first fields and the second one of the first fields are decoded using a first one of the sub-fields and a second one of the sub-fields respectively,
when the instruction decoder decodes a second very long instruction word, the second one of the first fields and the third one of the first fields are decoded using the first one of the sub-fields and the second one of the sub-fields respectively, and
the first and second very long instruction words are different from each other.

4. The VLIW processor according to claim 1 ,
wherein, when a certain one of the sub-fields in the second field is referred to by a certain one of the first fields, the certain one of the sub-fields is used to designate an operand for the operation designated by the certain one of the first fields.

5. The VLIW processor according to claim 4 ,
wherein, when the instruction register holds a first very long instruction word, a first one of the sub-fields and a second one of the sub-fields in the second field are referred to by a first one of the first fields and a second one of the first fields respectively, and the first one of the sub-fields and the second one of the sub-fields are used to designate operands for the operations designated by the first one of the first fields and the second one of the first fields respectively, and
when the instruction register holds a second very long instruction word, the first one of the sub-fields and the second one of the sub-fields in the second field are referred to by the second one of the first fields and a third one of the first fields respectively, and the first one of the sub-fields and the second one of the sub-fields are used to designate operands for the operations designated by the second one of the first fields and the third one of the first fields respectively.

6. The VLIW processor according to claim 1 , further comprising:
a register file having a plurality of registers,
wherein a certain one of the first fields includes an operational code and an operand code, and
a corresponding one of the operation units performs an operation specified by the operational code in the certain one of the first fields using a register in the register file which is specified by the operand code in the certain one of the first fields and a code in a certain one of the sub-fields.

7. The VLIW processor according to claim 6 ,
wherein the certain one of the sub-fields is specified by the certain one of the first fields.

8. The VLIW processor according to claim 1 ,
wherein the sub-fields in the second field to be correlated are designated by each of the first fields.

9. A very long instruction word (VLIW) processor which performs a plurality of operations in parallel, the VLIW processor comprising:
an instruction register for holding a very long instruction word; and
a plurality of operation units,
wherein the very long instruction word is composed of a plurality of first fields each designating an operation to be performed, and a second field partitioned into a plurality of sub-fields,
each of the first fields is decoded selectively with the sub-fields in the second field, the sub-fields to be decoded being designated by each of the first fields based on the very long instruction word held in the instruction register, and
multiple operations defined by the plurality of first fields and the second field are performed in parallel by the plurality of operation units.

10. The VLIW processor according to claim 9 ,
wherein the sub-fields used for decoding one of the first fields is determined in accordance with the very long instruction word held in the instruction register.

11. The VLIW processor according to claim 9 ,
wherein, when a certain one of the first fields is decoded with using one or more of the sub-fields, the certain one of the first fields designates the one or more of the sub-fields to be used for decoding.

12. The VLIW processor according to claim 9 , further comprising:
an instruction decoder for decoding the very long instruction word held in the instruction register,
wherein the instruction decoder is operable to decode each of the first fields in parallel, and
the decoding of each of the first fields is performed without using the sub-fields or is performed using at least one of the sub-fields in the second field selectively.

13. The VLIW processor according to claim 9 ,
wherein, when a certain one of the sub-fields in the second field is used for decoding a certain one of the first fields, the certain one of the sub-fields is used to designate an operand for the operation designated by the certain one of the first fields.

14. The VLIW processor according to claim 9 , further comprising:
a register file having a plurality of registers,
wherein a certain one of the first fields includes an operational code and an operand code, and
a corresponding one of the operation units performs an operation specified by the operational code in the certain one of the first fields using a register in the register file which is selectively specified by the operand code in the certain one of the first fields or specified by the operand code in the certain one of the first fields and a code in the sub-fields.

15. The VLIW processor according to claim 14 ,
wherein, when a certain one of the first fields is decoded with using a certain one of the sub-fields, the register which is used for the operation is specified by the operand code in the certain one of the first fields and a code in the certain one of the sub-fields.

Assignees

• Panasonic Corp
• Socionext Inc

Inventors

• Kageyama Takahiro
• Nishida Hideshi
• Tanaka Takeshi
• Nakajima Kouji

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30156 Primary

  Special purpose encoding of instructions, e.g. Gray coding · CPC title