Providing service address space for diagnostics collection

Patent metadata

Field	Value
Publication number	US-9696925-B2
Application number	US-201615249221-A
Country	US
Kind code	B2
Filing date	Aug 26, 2016
Priority date	Aug 10, 2012
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor wherein the main processor is provided with a main address space. The service address space and the main address space include a full range of memory available to the respective service-co-processor and the main processor. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor has a storage update receiving component for updating the service address space by receiving storage delta packets from the main processor and applying these to the service address space.

First claim

What is claimed is:

1. A system for providing service address space for diagnostics collection, comprising:
a service co-processor provided with a service address space, the service co-processor attached to a main processor wherein the main processor is provided with a main address space, wherein the service co-processor creates and maintains an independent copy of the main address space in the form of the service address space; and
wherein the main processor has an instruction intercepting component for intercepting instructions that modify the main address space, and wherein the main processor has a storage delta packet generator component for generating storage delta packets based on intercepted instructions; and
wherein the service co-processor has a storage update receiving component for updating the service address space by receiving the storage delta packets from the main processor and applying these to the service address space.

2. The system of claim 1 , further comprising an instruction pipe between the main processor and the service co-processor.

3. The system of claim 1 , wherein the main processor comprises a service delegation component for delegating collection of diagnostic data to the co-processor by sending a collection command from the main processor to the service co-processor for collection of data from the service address space.

4. The system of claim 1 , further comprising a command pipe between the main processor and the service co-processor.

5. The system of claim 1 , further comprising a service address space resetting component at the service co-processor for resetting the service address space by copying the main address space.

6. The system of claim 1 , wherein the service co-processor runs asynchronously to the main processor with the storage delta packets queued in an instruction pipe.

7. A system for providing service address space for diagnostics collection, comprising:
a service co-processor provided with a service address space, the service co-processor attached to a main processor wherein the main processor is provided with a main address space, the service address space and the main address space being a full range of memory available to the respective service co-processor and the main processor, wherein the service co-processor creates and maintains an independent copy of the main address space in the form of the service address space; and
wherein the service co-processor has a storage update receiving component for updating the service address space by receiving storage delta packets from the main processor and applying these to the service address space.

8. The system of claim 7 , wherein the service co-processor is attached to the main processor via an instruction pipe and a command pipe.

9. The system of claim 8 , wherein the main processor includes a service delegation component for delegating collection of diagnostic data to the co-processor by sending a collection command via the command pipe from the main processor to the service co-processor for collection of data from the service address space.

10. The system of claim 7 , wherein the main processor has an instruction intercepting component for intercepting instructions that modify the main address space.

11. The system of claim 7 , wherein the main processor has a storage delta packet generator component for generating the storage delta packets.

12. A computer program product for providing a service address space, the computer program product comprising a non-transitory computer readable medium having program instructions embodied therewith, the program instructions executable by a service co-processor to cause the service co-processor to:
create and maintain an independent copy of a main address space of a main processor in the form of a service address space, the service address space and the main address space being a full range of memory available to the respective service-co-processor and the main processor;
receive storage delta packets from the main processor; and
apply the storage delta packets to the service address space.

13. The computer program product of claim 12 , wherein the program instructions are executable by the service co-processor to cause the service co-processor to receive a collection command from the main processor to delegate collection of diagnostic data to the service co-processor.

14. The computer program product of claim 12 , wherein the program instructions are executable by the main processor to cause the main co-processor to:
monitor for instructions that modify the main address space;
generate the storage delta packets; and
send the storage delta packets on an instruction pipe to the service co-processor.

15. The computer program product of claim 12 , wherein the program instructions are executable by the service co-processor to cause the service co-processor to reset the service address space by copying the main address space.

Assignees

• IBM

Inventors

• Harman David J
• Leedham Neil W
• Walsh Kim P
• Wright Andrew

Classifications

• G06F11/0724 Primary

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title