Low defect density lattice-mismatched semiconductor devices and methods of fabricating same
US-9269569-B1 · Feb 23, 2016 · US
US9696486B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9696486-B2 |
| Application number | US-201313955705-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 31, 2013 |
| Priority date | Jul 31, 2013 |
| Publication date | Jul 4, 2017 |
| Grant date | Jul 4, 2017 |
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A photonic integrated circuit (PIC) is described. This PIC includes an inverse facet mirror on a silicon optical waveguide for optical proximity coupling between two silicon-on-insulator (SOI) chips placed face to face. Accurate mirror facets may be fabricated in etch pits using a silicon micro-machining technique, with wet etching of the silicon <110> facet at an angle of 45° when etched through the <100> surface. Moreover, by filling the etch pit with polycrystalline silicon or another filling material that has an index of refraction similar to silicon (such as a silicon-germanium alloy), a reflecting mirror with an accurate angle can be formed at the end of the silicon optical waveguide using: a metal coating, a dielectric coating, thermal oxidation, or selective silicon dry etching removal of one side of the etch pit to define a cavity.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit, comprising: a substrate; a buried-oxide layer disposed on the substrate; a semiconductor layer, disposed on the buried-oxide layer, having a top surface, wherein the semiconductor layer includes an etch pit having sides defined by a crystallographic plane of the semiconductor layer, wherein the etch pit extends from the top surface to the buried-oxide layer, wherein one of the sides includes a mirror facet, wherein the semiconductor layer is included in an optical waveguide configured to convey an optical signal, and wherein the integrated circuit includes an oxide layer disposed on the semiconductor layer underneath the mirror facet; and a filling material disposed in the etch pit. 2. The integrated circuit of claim 1 , wherein the substrate, the buried-oxide layer and the semiconductor layer comprise a silicon-on-insulator technology. 3. The integrated circuit of claim 1 , wherein the semiconductor layer includes silicon. 4. The integrated circuit of claim 1 , wherein the sides are at an angle with respect to the top surface; and wherein the angle is associated with the crystallographic plane. 5. The integrated circuit of claim 4 , wherein the angle includes one of: 45°, and an angle corresponding to the crystallographic plane and a tilt angle of the substrate during fabrication of the etch pit. 6. The integrated circuit of claim 1 , wherein the etch pit is fabricated using a wet-etching process. 7. The integrated circuit of claim 1 , wherein the filling material includes one of: polycrystalline silicon, a silicon-germanium alloy, and a material having an index of refraction that approximately matches an index of refraction of the semiconductor layer. 8. A system, comprising: two integrated circuits having top surfaces that face each other, wherein the integrated circuits are configured to convey an optical signal between the integrated circuits using surface-normal optical proximity communication, and wherein a given one of the integrated circuits includes: a substrate; a buried-oxide layer disposed on the substrate; a semiconductor layer, disposed on the buried-oxide layer, having a top surface, wherein the semiconductor layer includes an etch pit having sides defined by a crystallographic plane of the semiconductor layer, wherein the etch pit extends from the top surface to the buried-oxide layer, wherein one of the sides includes a mirror facet, wherein the semiconductor layer is included in an optical waveguide configured to convey an optical signal, and wherein the integrated circuit includes an oxide layer disposed on the semiconductor layer underneath the mirror facet; and a filling material disposed in the etch pit. 9. The system of claim 8 , wherein the substrate, the buried-oxide layer and the semiconductor layer comprise a silicon-on-insulator technology. 10. The system of claim 8 , wherein the sides are at an angle with respect to the top surface; and wherein the angle is associated with the crystallographic plane. 11. The system of claim 8 , wherein the filling material includes one of: polycrystalline silicon, a silicon-germanium alloy, and a material having an index of refraction that approximately matches an index of refraction of the semiconductor layer.
Mirror; Reflectors or the like · CPC title
Basic optical elements, e.g. light-guiding paths · CPC title
Etching · CPC title
the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device (G02B6/4246 takes precedence) · CPC title
Silicon · CPC title
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