Data receiving device including an envelope detector and related methods

Patent metadata

Field	Value
Publication number	US-9696351-B2
Application number	US-201414585357-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Dec 30, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

First claim

That which is claimed is:

1. A data receiving device comprising:
an envelope detector comprising
first and second inputs configured to receive a differential input signal,
a first pair of detectors comprising a first detector and a second detector, the first pair of detectors coupled to the first input and configured to generate first and second detector outputs,
a second pair of detectors comprising a third detector and a fourth detector, the second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs, and
a logic circuit configured to generate a reset based upon the first and third detectors;
a receiver circuit coupled to said envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset; and
a first bit detection circuit coupled to said receiver circuit.

2. The data receiving device according to claim 1 wherein the receiver circuit comprises a negative threshold path configured to receive the second detector output, and a positive threshold path configured to receive the fourth detector output.

3. The data receiving device according to claim 2 wherein each of the negative and positive threshold paths includes a flip flop controlled by the reset.

4. The data receiving device according to claim 1 further comprising a respective pair of series coupled resistors coupled to each of said first and second pairs of detectors.

5. The data receiving device according to claim 4 wherein said second and fourth detectors each have a respective trigger voltage based upon the respective pair of series coupled resistors.

6. The data receiving device according to claim 1 wherein said first bit detection circuit is configured to generate an output based upon said first and third detectors.

7. The data receiving device according to claim 1 wherein said envelope detector further comprises at least one current source coupled to said first and second pairs of detectors.

8. The data receiving device according to claim 7 wherein said at least one current source comprises a plurality of current sources coupled in parallel.

9. The data receiving device according to claim 8 wherein said plurality of current sources comprise a fixed current source and a variable current source.

10. The data receiving device according to claim 7 wherein said envelope detector further comprises an amplifier coupled to said at least one current source.

11. A data receiving device comprising:
an envelope detector comprising
first and second inputs configured to receive a differential input signal,
a first pair of detectors comprising a first detector and a second detector, the first pair of detectors coupled to the first input and configured to generate first and second detector outputs,
a second pair of detectors comprising a third detector and a fourth detector, the second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs,
at least one current source coupled to said first and second pairs of detectors, and
a logic circuit configured to generate a reset based upon the first and third detectors;
a receiver circuit coupled to said envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, said receiver circuit comprising a negative threshold path configured to receive the second detector output and a positive threshold path configured to receive the fourth detector output; and
a first bit detection circuit coupled to said receiver circuit.

12. The data receiving device according to claim 11 wherein each of the negative and positive threshold paths includes a flip flop controlled by the reset.

13. The data receiving device according to claim 11 further comprising a respective pair of series coupled resistors coupled to each of said first and second pairs of detectors.

14. The data receiving device according to claim 13 said second and fourth detectors each have a respective trigger voltage based upon the respective pair of series coupled resistors.

15. The data receiving device according to claim 11 wherein said first bit detection circuit is configured to generate an output based upon said first and third detectors.

16. The data receiving device according to claim 11 wherein said at least one current source comprises a plurality of current sources coupled in parallel.

17. The data receiving device according to claim 16 wherein said plurality of current sources comprise a fixed current source and a variable current source.

18. The data receiving device according to claim 11 wherein said envelope detector further comprises an amplifier coupled to said at least one current source.

19. A method of making a data receiving device comprising:
forming an envelope detector comprising
coupling a first pair of detectors comprising a first detector and a second detector to a first input configured to receive a differential input signal, the first pair of detectors configured to generate first and second detector outputs,
coupling a second pair of detectors comprising a third detector and a fourth detector to a second input configured to receive a differential input, the second pair of detectors configured to generate third and fourth detector outputs, and
coupling a logic circuit to the first and third detectors for generating a reset based thereon;
coupling a receiver circuit to the envelope detector for generating an output based upon the second and fourth detectors along with the reset; and
coupling a first bit detection circuit to the receiver circuit.

20. The method according to claim 19 wherein the receiver circuit comprises a negative threshold path configured to receive the second detector output, and a positive threshold path configured to receive the fourth detector output.

21. The method according to claim 19 wherein forming the envelope detector further comprises coupling at least one current source to the first and second pairs of detectors.

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Daljeet
• Nandy Tapas
• Kumar Surendra

Classifications

• G01R19/04 Primary

  Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title

• G01R19/2503

  for measuring voltage only, e.g. digital volt meters (DVM's) (G01R19/2506 - G01R19/257 take precedence) · CPC title