Digital clock-duty-cycle correction

Patent metadata

Field	Value
Publication number	US-9692403-B2
Application number	US-201514927929-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element and a controller. The first programmable delay element is configured to delay a clock signal. The controller is configured to vary an amount of delay applied to the clock signal by the first programmable delay element, and to apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.

First claim

What is claimed is:

1. A clock generator, comprising:
a duty cycle correction circuit, comprising:
a duty cycle detector, comprising:
a first programmable delay element configured to delay a clock signal; and
a controller configured to:
vary an amount of delay applied to the clock signal by the first programmable delay element;
apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure the time during which the different version of the clock signal is high; and
generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on the measured time during which the different version of the clock signal is high;

wherein the controller is configured to:
apply the delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of the different version of the clock signal and measure the time during which the different version of the clock signal is low;
compare the time during which the different version of the clock signal is low to the time during which the different version of the clock signal is high; and

generate the digital value to reduce duration of a longer of the time during which the different version of the clock signal is low and the time during which the different version of the clock signal is high;
a multiplexer configured to selectably route a non-inverted version of the clock signal and an inverted version of the clock signal to the first programmable delay element for measurement of the time during which the different version of the clock signal is high and the time during which the different version of the clock signal is low.

2. A clock generator, comprising:
a duty cycle correction circuit, comprising:
a duty cycle detector, comprising:
a first programmable delay element configured to delay a clock signal; and
a controller configured to:
vary an amount of delay applied to the clock signal by the first programmable delay element;
apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure the time during which the different version of the clock signal is high; and

generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on the measured time during which the different version of the clock signal is high; and
a fixed delay element configured to delay the clock signal by a fixed predetermined amount to produce the different version of the clock signal.

3. The clock generator of claim 2 , wherein the fixed predetermined amount is equal to a minimum amount of delay generated by the first programmable delay element.

4. A clock generator, comprising:
a duty cycle correction circuit, comprising:
a duty cycle detector, comprising:
a first programmable delay element configured to delay a clock signal; and
a controller configured to:
vary an amount of delay applied to the clock signal by the first programmable delay element;
apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure the time during which the different version of the clock signal is high; and

generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on the measured time during which the different version of the clock signal is high; and
wherein the controller is configured to apply a successive approximation technique to vary an amount of delay applied to the clock signal by the first programmable delay element for measuring time during which the different version of the clock signal is high.

5. A clock generator, comprising:
a duty cycle correction circuit, comprising:
a duty cycle detector, comprising:
a first programmable delay element configured to delay a clock signal; and
a controller configured to:
vary an amount of delay applied to the clock signal by the first programmable delay element;
apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure the time during which the different version of the clock signal is high; and

generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on the measured time during which the different version of the clock signal is high;
a second programmable delay element coupled to the controller; and
a pulse width adjuster coupled to the second programmable delay element;
wherein the second programmable delay element is configured to delay a reference clock based on the digital value, and the pulse width adjuster is configured to set the duty cycle of the clock signal based on a delayed version of the reference clock provided by the second programmable delay element.

6. A clock duty cycle correction circuit comprising:
a duty cycle detector, comprising:
a detector delay element configured to delay a corrected clock signal by a programmable time;
a controller configured to:
vary an amount of delay applied to the corrected clock signal by the detector delay element; and
measure the duty cycle of the corrected clock signal based on a delayed version of the corrected clock signal produced by the detector delay element; and
generate a digital value that indicates an amount of adjustment to apply to the duty cycle of the corrected clock signal based on a measured duty cycle of the corrected clock signal; and

a duty cycle adjustor configured to change the duty cycle of the corrected clock signal responsive to a change in the digital value;
wherein the controller is configured to apply a delayed version of the clock signal, provided by the detector programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high; and
wherein the duty cycle detector comprises a fixed delay element configured to delay the corrected clock signal by a fixed predetermined amount to produce the different version of the clock signal.

7. The clock duty cycle correction circuit of claim 6 , wherein the fixed predetermined amount is equal to a minimum amount of delay generated by the detector programmable delay element.

8. A clock duty cycle correction circuit comprising:
a duty cycle detector, comprising:
a detector delay element configured to delay a corrected clock signal by a programmable time;
a controller configured to:
vary an amount of delay applied to the corrected clock signal by the detector delay element; and
measure the duty cycle of the corrected clock signal based on a delayed version of the corrected clock signal produced by the detector delay element; and
generate a digital value that indicates an amount of adjustment to apply to the duty cycle of the corrected clock signal based on a measured duty cycle of the corrected clock signal; and

a duty cycle adjustor configured to change the duty cycle of the corrected clock signal responsive to a change in the digital value;
wherein the duty cycle detector comprises a multiplexer configured to selectably route a non-inverted version of the corrected clock signal and an inverted version of the corrected clock signal to the detector programmable delay element for measurement of a time during which the corrected clock signal is high and a time during which the corrected clock signal is low.

9. A clock du

Assignees

• Texas Instruments Inc

Inventors

• Elbadry Mohammad

Classifications

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title