Method, apparatus, system for centering in a high performance interconnect

Patent metadata

Field	Value
Publication number	US-9692402-B2
Application number	US-201414583139-A
Country	US
Kind code	B2
Filing date	Dec 25, 2014
Priority date	Dec 25, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

First claim

What is claimed is:

1. An interconnect apparatus comprising:
a clock generator to generate a clock signal at a low speed for the interconnect;
a phase shifter to phase shift the clock signal by a first test phase;
an error rate detector to measure an error rate of the test phase;
the phase shifter is further to shift the clock signal by a second test phase;
the error rate detector is further to measure an error of the second test phase;
an error comparator to compare the error rate of the first test phase to the error rate of the second test phase and to select an optimal test phase;
an operational phase selector to select the operational phase of the clock signal based at least in part on the optimal test phase;
a reference voltage shifter to shift a reference voltage by a test voltage at an operational speed of the interconnect;
the error rate detector is further to measure an error rate of the test voltage; and
an operational voltage selector to select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage.

2. The interconnect apparatus of claim 1 , wherein the phase shifter is a quantized phase shifter.

3. The interconnect apparatus of claim 1 , wherein:
the test voltage is a first test voltage;
the reference voltage shifter is further to shift the reference voltage by a second test voltage;
the error comparator is further to compare the error rate of the first test voltage to an error rate of the second test voltage and to select an optimal test voltage; and
wherein the operational voltage selector selects an operational voltage of the clock signal based at least in part on the first test voltage by selecting the operational reference voltage of the clock signal based at least in part on the optimal test voltage.

4. The interconnect apparatus of claim 3 , further comprising an eye constructor, and a two-dimensional factor shifter; wherein:
the eye constructor is to construct an eye based at least in part on the optimal phase and the optimal voltage;
the two dimensional factor shifter is to select first and second phase and voltage pairs within the eye;
the error rate detector is further to measure an error rate for each of the first and second phase and voltage pairs; and
the error rate detector is further to compare the error rate of the first phase and voltage pair to the error rate of the second phase and voltage pair, and select an optimal phase and voltage pair.

5. The interconnect apparatus of claim 1 , wherein the error rate detector measures the error rate by receiving a test pattern onto a first lane, and a crosstalk pattern on at least one adjacent lane.

6. The interconnect apparatus of claim 5 , wherein the crosstalk pattern is a logical inverse of the test pattern.

7. An interconnected system, comprising:
a first agent;
a second agent; and
an interconnect to communicatively couple the first agent to the second agent, comprising:
a clock generator to generate a clock signal at a low speed for the interconnect;
a phase shifter to phase shift the clock signal by a test phase;
an error rate detector to measure an error rate of the test phase;
the phase shifter is further to shift the clock signal by a second test phase;
the error rate detector is further to measure an error of the second test phase;
an error comparator to compare the error rate of the first test phase to the error rate of the second test phase and to select an optimal test phase;
an operational phase selector to select an operational phase of the clock signal based at least in part on the optimal test phase;
a reference voltage shifter to shift a reference voltage by a test voltage;
the error rate detector is further to measure an error rate of the test voltage at an operational speed for the interconnect; and
an operational voltage selector to select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage.

8. The interconnected system of claim 7 , wherein the phase shifter is a quantized phase shifter.

9. The interconnected system of claim 7 , wherein:
the test voltage is a first test voltage;
the reference voltage shifter is further to shift the reference voltage by a second test voltage;
the error comparator is further to compare the error rate of the first test voltage to an error rate of the second test voltage and to select an optimal test voltage; and
wherein the operational voltage selector selects the operational voltage of the clock signal based at least in part on the first test voltage by selecting the operational voltage of the clock signal based at least in part on the optimal test voltage.

10. The interconnected system of claim 9 , wherein the interconnect further comprises an eye constructor and a two-dimensional factor shifter; wherein:
the eye constructor is to construct an eye based at least in part on the optimal test phase and the optimal reference voltage;
the two-dimensional factor shifter is to select first and second phase and voltage pairs within the eye;
the error rate detector is further to measure an error rate for each of the first and second phase and voltage pairs; and
the error rate detector is further to compare the error rate of the first phase and voltage pair to the error rate of the second phase and voltage pair, and select an optimal phase and voltage pair.

11. The interconnected system of claim 7 , wherein the first agent is to drive a first pattern onto a first lane and a crosstalk pattern onto a second lane, and wherein the error rate detector measures the error rate by sampling the first pattern.

12. The interconnected system of claim 11 , wherein the crosstalk pattern is a logical inverse of the test pattern.

13. One or more tangible, non-transitory computer-readable mediums having stored thereon executable instructions to:
generate a clock signal;
phase shift the clock signal by a quantized test phase at a low speed for an interconnect;
detect an error rate of the test phase;
shift the clock signal by a second test phase;
measure an error of the second test phase;
compare the error rate of the first test phase to the error rate of the second test phase and select an optimal test phase;
select an operational phase of the clock signal based at least in part on the optimal test phase;
shift a reference voltage by a test voltage;
measure an error rate of the test voltage at an operational speed for the interconnect; and
select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage.

14. The one or more computer-readable mediums of claim 13 , wherein the test voltage is a first test voltage, and the instructions are further to:
shift the reference voltage by a second test voltage;
compare the error rate of the first test voltage to an error rate of the second test voltage and select an optimal test voltage; and
select the operational reference voltage of the clock signal based at least in part on the first test voltage by selecting the operational voltage of the clock signal based at least in part on the optimal test voltage.

15. The one or more computer-readable mediums of claim 14 , wherein the instructions are further to:
construct an eye based at least in part on the optimal test phase and the optimal test voltage;
select first and second phase and voltage pairs within the eye;
measure an error rate for each of the first and second phase and voltage pairs; and
compare the error rate of the first phase and voltage pair to the error rate o

Assignees

• Intel Corp

Inventors

• Wagh Mahesh
• Wu Zuoguo
• Iyer Venkatraman
• Pasdast Gerald S
• Hinck Todd A
• Lee David M
• Lanka Narasimha R

Classifications

• H03K5/131

  Digitally controlled · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• G01R31/67

  Testing the correctness of wire connections in electric apparatus or circuits · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title