Three-dimensional wire bond inductor

Patent metadata

Field	Value
Publication number	US-9692386-B2
Application number	US-201414177620-A
Country	US
Kind code	B2
Filing date	Feb 11, 2014
Priority date	Dec 23, 2013
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

An inductor is provided on a substrate that includes a capacitor. The inductor comprises a series of wire loops. An end of the wire loop is wire bonded to the capacitor.

First claim

We claim:

1. An apparatus, comprising:
a substrate including a surface;
a capacitor integrated with the substrate, the capacitor including a metal plate adjacent the surface;
a series of wire loops configured to project from the surface with each wire loop forming an arch extending above the surface; and
planar inductor connecting portions on the surface and configured to couple the wire loops to form an inductor; and
wherein the inductor extends from a first end of a first one of the series of wire loops to a second end of a last one of the series of wire loops, wherein the first end of the first wire loop forms a first terminal of the inductor and the second end of the last one of the series of wire loops forms a second terminal of the inductor, and further wherein the first terminal of the inductor is bonded directly to the metal plate of the capacitor.

2. The apparatus of claim 1 , further comprising a first inductor connecting portion of the planar inductor connecting portions that is adjacent the surface, wherein a second end of the first wire loop is wire bonded to the first inductor connecting portion, and wherein a first end of a second one of the wire loops is wire bonded to the first inductor connecting portion and further wherein the first inductor connecting portion forms part of the inductor.

3. The apparatus of claim 2 , wherein:
the first inductor connecting portion of the planar inductor connecting portions has a first thickness of at least 20 microns; and
the metal plate of the capacitor has a second thickness of between 2 and 3 microns.

4. The apparatus of claim 1 , wherein at least one of the planar inductor connecting portions has a length greater than a width of the inductor.

5. The apparatus of claim 1 , wherein opposing ends of at least one of the planar inductor connecting portions are offset relative to one another along an axis of the inductor.

6. The apparatus of claim 1 , wherein the series of wire loops form a truncated spiral shape.

7. The apparatus of claim 1 , further comprising a pad on the surface of the substrate, wherein the end of the last wire loop is bonded to the pad.

8. The apparatus of claim 1 , wherein an end of at least one loop in the series of wire loops is connected across an axis of the inductor to an end of an adjacent loop in the series of wire loops by a corresponding planar inductor portion of the planar inductor connecting portions.

9. The apparatus of claim 1 , wherein the metal plate comprises a second metal layer exposed on a dielectric layer, the capacitor further comprising:
a first metal layer on the surface of the substrate; and
the dielectric layer disposed between the first metal layer and the second metal layer.

10. The apparatus of claim 1 , wherein none of the planar inductor connecting portions is perpendicular to an axis of the inductor.

11. The apparatus of claim 1 , wherein the center of at least one wire loop in the series of wire loops is aligned along an axis of the inductor.

12. The apparatus of claim 1 , wherein the substrate is a passivation layer.

13. The apparatus of claim 1 , wherein the wire loops are configured so that a magnetic field induced by current flowing through each wire loop reinforces a magnetic field produced by the other wire loops of the series of wire loops.

14. The apparatus of claim 1 , wherein the metal plate of the capacitor is relatively thin compared to the planar inductor connecting portions.

15. A method, comprising:
forming a capacitor on a substrate, wherein forming the capacitor includes forming a metal plate;
forming an inductor on the substrate, wherein forming the inductor includes forming a series of wire-bonded loops with each wire loop forming an arch extending above a surface of the substrate, and
forming planar inductor connecting portions on the surface and configured to couple the wire loops to form the inductor, wherein the inductor extends from a first terminal at a first end of a first wire loop to a second terminal at a second end of a last wire loop on the substrate; and
bonding the first end of the first wire loop directly to the metal plate.

16. The method of claim 15 , further comprising depositing a dielectric layer on a surface of the substrate and then electroplating an inductor connecting portion of the planar inductor connecting portions on a surface of the dielectric layer, wherein forming the inductor comprises wire bonding a second end of the first wire loop to the inductor connecting portion and wire bonding a first end of a second wire loop to the inductor connecting portion and further wherein the inductor connecting portion forms part of the inductor.

17. The method of claim 15 , wherein the metal plate of the capacitor is formed to be relatively thin compared to the planar inductor connecting portions.

18. The method of claim 15 , wherein opposing ends of at least one of the planar inductor connecting portions are formed to be offset relative to one another along an axis of the inductor.

19. The method of claim 15 , wherein the series of wire loops are formed into a truncated spiral shape.

20. The method of claim 15 , wherein an end of at least one loop in the series of wire loops is formed to connect across an axis of the inductor to an end of an adjacent loop in the series of wire loops by a corresponding planar inductor portion of the planar inductor connecting portions.

21. The method of claim 15 , wherein none of the planar inductor connecting portions is formed perpendicular to an axis of the inductor.

22. The method of claim 15 , wherein the center of at least one wire loop in the series of wire loops is formed to be aligned along an axis of the inductor.

23. The method of claim 15 , wherein the substrate is formed as a passivation layer.

24. The method of claim 15 , wherein the wire loops are formed so that a magnetic field induced by current flowing through each wire loop reinforces a magnetic field produced by the other wire loops of the series of wire loops.

25. The method of claim 15 , wherein forming the capacitor comprises:
depositing a first metal layer on a surface of the substrate;
depositing a dielectric layer on the first metal layer;
depositing a second metal layer on the dielectric layer, wherein the metal plate comprises the second metal layer; and
exposing the second metal layer of the dielectric layer.

26. The method of claim 25 , wherein depositing the first and second metal layers comprises sputtering, and wherein bonding the first end of the first wire loop comprises wire bonding the first terminal of the inductor to the metal plate and wire bonding the second terminal of the inductor to a pad.

27. The method of claim 15 , wherein at least one of the planar inductor connecting portions is formed to have a length greater than a width of the inductor.

28. A resonant tank circuit, comprising:
a substrate;
a capacitor;
an inductor including a plurality of wire loops arranged from a first wire loop to a last wire loop with each wire loop forming an arch extending above a surface of the substrate, and planar inductor connecting portions on the surface of the substrate and configured to couple the wire loops to form the inductor, wherein a terminal of the first wire loop is wire bonded directly to the capacitor; and
wherein the capacitor and at least a portion of the inductor are

Assignees

• Qualcomm Inc

Inventors

• Zuo Chengjie
• Velez Mario Francisco
• Kim Jonghae
• Kim Daeik Daniel
• Yun Changhan Hobie

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title