FinFET cell architecture with power traces

Patent metadata

Field	Value
Publication number	US-9691764-B2
Application number	US-201514923140-A
Country	US
Kind code	B2
Filing date	Oct 26, 2015
Priority date	Jul 29, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a first set of semiconductor fins in a first region of the substrate;
a plurality of gate traces overlying the first set;
a patterned conductor layer overlying the first set, including;
a first patterned conductor over the first set and connected to source/drain regions of two or more fins in the first set, and
a second patterned conductor over the first set and connected to source/drain regions of one or more fins in the first set,
wherein the first patterned conductor is connected to more source/drain regions of fins in the first set than the second patterned conductor.

2. The integrated circuit of claim 1 , wherein the plurality of gate traces are arranged in columns, and source/drain regions of the fins in the first set are arranged in columns adjacent to the columns of gate traces, and
wherein the first region includes fine granularity with partial usage of the source/drain columns across the first region.

3. The integrated circuit of claim 1 , wherein the source/drain regions connected to the first patterned conductor make up a terminal of a first device having a gate in a first gate trace in the plurality of gate traces, and
wherein the source/drain regions connected to the second patterned conductor make up a terminal of a second device having a gate in a second gate trace in the plurality of gate traces.

4. The integrated circuit of claim 1 , wherein the source/drain regions connected to the first patterned conductor make up a terminal of a first device having a gate in a first gate trace in the plurality of gate traces, and
wherein the source/drain regions connected to the second patterned conductor make up a terminal of a second device having a gate in the first gate trace.

5. The integrated circuit of claim 1 , wherein the source/drain regions connected to the first patterned conductor make up a first terminal of a first device having a gate in a first gate trace in the plurality of gate traces,
wherein the source/drain regions connected to the second patterned conductor make up a first terminal of a second device having a gate in a second gate trace in the plurality of gate traces, and
wherein the first and second gate traces are adjacent and source/drain regions, of the fins, between the first and second gate traces make up a second terminal of the first device and a second terminal of the second device.

6. The integrated circuit of claim 1 , wherein the first patterned conductor is connect to a first source/drain region of a first fin in the first set, and
wherein the second patterned conductor is connected to a second source/drain region of the first fin.

7. The integrated circuit of claim 1 , further including
a second set of semiconductor fins in a second region of the substrate, wherein the second set is parallel to the first set;
wherein the plurality of gate traces includes a plurality of gate traces over the second set;
wherein at least one of the first or second patterned conductors is connected to source/drain regions of one or more fins in the second set.

8. An integrated circuit, comprising:
a substrate;
a first set of semiconductor fins in a first region of the substrate;
a second set of semiconductor fins in a second region of the substrate;
a first isolation feature parallel to and between the first and second sets of semiconductor fins;
a patterned gate conductor layer including a plurality of first region gate traces overlying the first set, a plurality of second region gate traces overlying the second set;
a patterned conductor layer overlying the first and second sets, including;
a first patterned conductor over the first and second sets and connected to source/drain regions of one or more fins in the first set and connected to source/drain regions of one or more fins in the second set;
wherein the first patterned conductor is connected to more source/drain regions of fins in the first set than source/drain regions of fins in the second set.

9. The integrated circuit of claim 8 , wherein the plurality of first region gate traces and second gate traces are arranged in columns, and source/drain regions of the fins in the first and second sets are arranged in columns adjacent to the columns of gate traces, and
wherein the first or second region includes fine granularity with partial usage of the source/drain columns across the first or second region.

10. The integrated circuit of claim 8 , wherein the first set and second set have a different number of fins.

11. A method for manufacturing a cell library, comprising:
specifying a base structure in a computer readable memory, the base structure comprising a first set of semiconductor fins in a first region of a substrate;
specifying a cell by combining elements of the cell with the base structure in a computer readable format, the cell comprising elements of:
a plurality of gate traces overlying the first set, and
a patterned conductor layer overlying the first set, the patterned conductor layer including
a first patterned conductor over the first set and connected to source/drain regions of two or more fins in the first set, and
a second patterned conductor over the first set and connected to source/drain regions of one or more fins in the first set,

wherein the first patterned conductor is connected to more source/drain regions of fins in the first set than the second patterned conductor; and

storing a machine readable specification of the cell in the cell library in non-transitory memory.

12. The method for manufacturing and using a cell library of claim 11 , wherein the plurality of gate traces are arranged in columns, and source/drain regions of the fins in the first set are arranged in columns adjacent to the columns of gate traces, and
wherein the first region includes fine granularity with partial usage of the source/drain columns across the first region.

13. A method for manufacturing a cell library, comprising:
specifying a base structure in a computer readable format in non-transitory memory, the base structure comprising:
a first set of semiconductor fins in a first region of a substrate, the first set being arranged for devices having channels with a first conductivity type,
a second set of semiconductor fins in a second region of the substrate, the second set being arranged for devices having channels with a second conductivity type, and
a first isolation feature parallel to and between the first and second sets of semiconductor fins;

specifying a cell by combining elements of the cell with the base structure in a computer readable format, the cell comprising elements of:
a patterned gate conductor layer including a plurality of first region gate traces overlying the first set and a plurality of second region gate traces overlying the second set,
a patterned conductor layer overlying the first and second sets, including a first patterned conductor over the first and second sets and connected to source/drain regions of one or more fins in the first set and connected to source/drain regions of one or more fins in the second set;
wherein the first patterned conductor is connected to more source/drain regions of fins in the first set than source/drain regions of fins in the second set; and

storing a machine readable specification of the cell in the cell library in non-transitory memory.

14. The method for manufacturing and using a cell library of claim 13 , wherein the plurality of first region gate traces and second gate traces are arranged in columns, and source/drain regions of the fins in the first and seco

Assignees

• Synopsys Inc

Inventors

• Kawa Jamil
• Moroz Victor
• Sherlekar Deepak D

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5068

  Physics · mapped topic