Integrated semiconductor device and wafer level method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9691725-B2
Application number	US-201615076003-A
Country	US
Kind code	B2
Filing date	Mar 21, 2016
Priority date	Jul 31, 2012
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.

First claim

What is claimed is:

1. A device comprising:
a first semiconductor substrate having a first side and an opposing second side;
a first electrical device embedded in the first semiconductor substrate adjacent the first side of the semiconductor substrate;
a first bonding pad disposed over the first side of the first semiconductor substrate, wherein the first bonding pad is electrically coupled to the first electrical device;
a second semiconductor substrate having a third side and an opposing fourth side;
a second bonding pad disposed over the third side of the second semiconductor substrate, wherein the first and second semiconductor substrates are bonded together via the first bonding pad and the second bonding pad such that the first side of the first semiconductor substrate faces the third side of the second semiconductor substrate;
a through-substrate-via (“TSV”) extending from the second side of the first semiconductor substrate to the first bonding pad, wherein the TSV includes a trench extending from the second side of the first semiconductor substrate to the first bonding pad and a metal material layer disposed within the trench;
an insulating layer disposed over the second side of the first semiconductor substrate; and
a first passivation layer disposed over the insulating layer over the second side of the first semiconductor substrate, and
wherein the metal material layer disposed within the trench includes opposing sidewall portions and the first passivation layer extends within the trench between the opposing sidewall portions of the metal material layer.

2. The device of claim 1 , further comprising a second electrical device embedded in the second semiconductor substrate adjacent the third side of the semiconductor substrate, wherein the second electrical device is electrically connected to the second bonding pad.

3. The device of claim 2 , wherein the first electrical device includes a capacitor, and
wherein the second electrical device includes a complementary metal-oxide-semiconductor device.

4. The device of claim 1 , further comprising:
a second passivation layer disposed over the first side of the first semiconductor substrate between the first bonding pad and the first side of the first semiconductor substrate; and
a third passivation layer disposed over the third side of the second semiconductor substrate between the second bonding pad and the third side of the second semiconductor substrate.

5. The device of claim 4 , wherein the second passivation layer physically contacts the third passivation layer.

6. The device of claim 4 , wherein the second passivation layer does not physically contact the third passivation layer.

7. The device of claim 4 , wherein the second passivation layer includes a first interconnect structure and the third passivation layer includes a second interconnect structure, and
wherein the first and second interconnect structures are electrically coupled.

8. The device of claim 1 , further comprising another insulating layer disposed over the first side of the first semiconductor substrate such that at least a portion of the first bonding pad is embedded within the another insulating layer, and
wherein the first passivation layer extends into the another insulating layer.

9. The device of claim 1 , wherein first passivation layer physically contacts the second side of the first semiconductor substrate.

10. A device comprising:
a first semiconductor substrate having a first side and an opposing second side;
a first bonding pad disposed over the first side of the first semiconductor substrate;
a second semiconductor substrate having a third side and an opposing fourth side;
a second bonding pad disposed over the third side of the second semiconductor substrate, wherein the first and second semiconductor substrates are bonded together such that the first side of the first semiconductor substrate faces the third side of the second semiconductor substrate; and
a through-substrate-via (“TSV”) extending from the second side of the first semiconductor substrate to the first bonding pad, wherein the TSV includes:
a trench extending from the second side of the first semiconductor substrate to the first bonding pad;
a conductive material disposed within the trench and over the portion of the second side of the first semiconductor substrate, the conductive material disposed within the trench including opposing sidewall portions;
a passivation layer disposed within the trench and over the portion of the second side of the first semiconductor substrate, the passivation layer extending within the trench between the opposing sidewall portions of the conductive material; and
an insulating material disposed within the trench and over a portion of the second side of the first semiconductor substrate.

11. The device of claim 10 , wherein the passivation layer is disposed over the insulating material on the second side of the first semiconductor substrate such that the passivation layer is prevented from interfacing with the first semiconductor substrate by the insulating material.

12. The device of claim 10 , further comprising a third bonding pad disposed over the first side of the first semiconductor substrate; and
a conductive bonding material disposed over the third bonding pad, wherein the second bonding pad and the third bonding pad physically contact the conductive bonding material.

13. The device of claim 10 , further comprising a first insulating layer disposed over the first side of the first semiconductor substrate between the first bonding pad and the first side of the first semiconductor substrate; and
a second insulting layer disposed over the third side of the second semiconductor substrate between the second bonding pad and the third side of the second semiconductor substrate.

14. The device of claim 13 , wherein the first bonding pad is at least partially embedded within the first insulating layer.

15. The device of claim 13 , wherein the passivation layer extends into the first insulating layer.

16. A device comprising:
a first semiconductor substrate having a first side and an opposing second side;
a first bonding pad disposed over the first side of the first semiconductor substrate;
a second semiconductor substrate having a third side and an opposing fourth side;
a second bonding pad disposed over the third side of the second semiconductor substrate, wherein the first and second semiconductor substrates are bonded together such that the first side of the first semiconductor substrate faces the third side of the second semiconductor substrate;
a first insulating layer disposed over the first side of the first semiconductor substrate such that at least a portion of the first bonding pad is embedded within the first insulating layer;
a second insulting layer disposed over the third side of the second semiconductor substrate between the second bonding pad and the third side of the second semiconductor substrate; and
a through-substrate-via (“TSV”) extending from the second side of the first semiconductor substrate to one of the first and second bonding pads, wherein the TSV includes:
a trench extending from the second side of the first semiconductor substrate to one of the first and second bonding pads;
a conductive material disposed within the trench and over the portion of the second side of the first semiconductor substrate, the conductive material disposed within the trench including opposing sidewall portions; and
a passivation layer disposed within the trench and over the portion of the second side of the fi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Kuei-Sung
• Cheng Chun-Wen
• Kalnitsky Alexander
• Chu Chia-Hua

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title