Semiconductor device security

Patent metadata

Field	Value
Publication number	US-9691709-B2
Application number	US-201514632507-A
Country	US
Kind code	B2
Filing date	Feb 26, 2015
Priority date	Feb 26, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

Semiconductor device security is provided as follows. A unique identification is generated by randomly forming a plurality of defects in one or more circuit elements of the semiconductor device. This method may yield a semiconductor device which is not susceptible to being replicated or cloned.

First claim

What is claimed is:

1. An integrated circuit comprising:
one or more circuit elements;
wherein the one or more circuit elements comprise a plurality of defects formed in the one or more circuit elements to generate an identification uniquely associated with the integrated circuit;
wherein the identification is generated by forming the plurality of defects in the one or more circuit elements in a plurality of random locations;
wherein at least one of the plurality of defects is formed by a direct e-beam write in a via thereby preventing electrical conductivity there through.

2. The integrated circuit of claim 1 , wherein the plurality of defects prevent operation of the one or more circuit elements.

3. The integrated circuit of claim 1 , wherein the at least one of the plurality of defects comprises contamination deposited in the via.

4. The integrated circuit of claim 3 , wherein the contamination comprises a carbon layer.

5. The integrated circuit of claim 1 , wherein the identification is at least one of non-clonable and non-replicable.

6. The integrated circuit of claim 1 , wherein the plurality of detects are located in at least one of a cache area and a core area of the integrated circuit.

7. The integrated circuit of claim 1 , wherein the identification is readable by scanning the semiconductor device.

8. The integrated circuit of claim 7 , wherein scanning the semiconductor device comprises writing a predetermined data pattern into an entirety of memory and then reading the entirety of the memory to detect failed memory bits.

9. The integrated circuit of claim 8 , wherein the identification is represented by each location of the failed memory bits.

10. The integrated circuit of claim 1 , wherein the identification represents a secure encryption key.

11. The integrated circuit of claim 1 , wherein the plurality of defects are formed after via patterning and before subsequent metallization processes.

12. The integrated circuit of claim 1 , wherein the plurality of random locations is associated with a plurality of random numbers produced by a random number generator.

13. The integrated circuit of claim 1 , wherein the direct e-beam write leaves a non-conductive material in the via.

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H10P74/20

  characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

• H10P34/40

  with high-energy radiation · CPC title

• H10P14/6902

  composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

• H10D64/01332

  Making the insulator · CPC title

• H10W46/403

  for non-wireless electrical read out · CPC title