Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

Patent metadata

Field	Value
Publication number	US-9691698-B2
Application number	US-201615205416-A
Country	US
Kind code	B2
Filing date	Jul 8, 2016
Priority date	Jan 14, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

First claim

That which is claimed is:

1. A method of making an electronic device comprising:
forming an interconnect layer stack on a glass substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers, with an uppermost patterned electrical conductor layer including at least one pad;
forming a liquid crystal polymer (LCP) substrate and comprising at least one electrical conductor via;
aligning the LCP substrate to the interconnect layer stack on a side thereof opposite the glass substrate, with the at least one electrical conductor via being aligned with the at least one pad of the uppermost patterned electrical conductor layer;
forming a fused seam directly between the interconnect layer stack and the LCP substrate, and while intermetallically bonding the at least one electrical conductor via to the uppermost patterned electrical conductor layer; and
removing the glass substrate.

2. The method of claim 1 , wherein removing the glass substrate exposes a lowermost patterned electrical conductor layer.

3. The method of claim 2 , further comprising electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

4. The method of claim 3 , wherein the at least one first device comprises a first integrated circuit (IC) die in a flip chip arrangement.

5. The method of claim 1 , wherein forming the fused seam and intermetallically bonding comprises applying heat and pressure to the LCP substrate and the interconnect layer stack.

6. The method of claim 5 , wherein applying heat and pressure is performed in an autoclave.

7. The method of claim 1 , wherein forming the interconnect layer stack comprises forming the plurality of patterned electrical conductor layers by thin film deposition.

8. The method of claim 1 , wherein the LCP substrate has a thickness of less than 0.0025 inches.

9. The method of claim 1 , wherein the glass substrate comprises an atomically smooth glass substrate.

10. A method of making an electronic device comprising:
forming an interconnect layer stack on a glass substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers, with an uppermost patterned electrical conductor layer including at least one pad;
forming a liquid crystal polymer (LCP) substrate and comprising at least one electrical conductor via;
aligning the LCP substrate to the interconnect layer stack on a side thereof opposite the glass substrate, with the at least one electrical conductor via being aligned with the at least one pad of the uppermost patterned electrical conductor layer;
using an autoclave to form a fused seam directly between the interconnect layer stack and the LCP substrate, and while intermetallically bonding the at least one electrical conductor via to the uppermost patterned electrical conductor layer; and
removing the glass substrate.

11. The method of claim 10 , wherein removing the glass substrate exposes a lowermost patterned electrical conductor layer.

12. The method of claim 11 , further comprising electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

13. The method of claim 12 , wherein the at least one first device comprises a first integrated circuit (IC) die in a flip chip arrangement.

14. The method of claim 10 , wherein forming the interconnect layer stack comprises forming the plurality of patterned electrical conductor layers by thin film deposition.

15. The method of claim 10 , wherein the LCP substrate has a thickness of less than 0.0025 inches.

16. The method of claim 10 , wherein the glass substrate comprises an atomically smooth glass substrate.

17. A method of making an electronic device comprising:
providing an interconnect layer stack on a glass substrate and comprising a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers, with an uppermost patterned electrical conductor layer including at least one pad;
providing a liquid crystal polymer (LCP) substrate and comprising at least one electrical conductor via;
aligning the LCP substrate to the interconnect layer stack on a side thereof opposite the glass substrate, with the at least one electrical conductor via being aligned with the at least one pad of the uppermost patterned electrical conductor layer;
forming a fused seam directly between the interconnect layer stack and the LCP substrate, and while intermetallically bonding the at least one electrical conductor via to the uppermost patterned electrical conductor layer; and
removing the glass substrate.

18. The method of claim 17 , wherein removing the glass substrate exposes a lowermost patterned electrical conductor layer.

19. The method of claim 18 , further comprising electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

20. The method of claim 19 , wherein the at least one first device comprises a first integrated circuit (IC) die in a flip chip arrangement.

21. The method of claim 17 , wherein forming the fused seam and intermetallically bonding comprises applying heat and pressure to the LCP substrate and the interconnect layer stack.

22. The method of claim 21 , wherein applying heat and pressure is performed in an autoclave.

23. The method of claim 17 , wherein the LCP substrate has a thickness of less than 0.0025 inches.

24. The method of claim 17 , wherein the glass substrate comprises an atomically smooth glass substrate.

Assignees

• Harris Corp

Inventors

• Weatherspoon Michael Raymond
• Nicol David B
• Rendek Jr Louis Joseph

Classifications

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/07551

  characterised by changes in properties of the bond wires during the connecting · CPC title

• H10W90/00

  Package configurations · CPC title