Multi-layer capacitor and method for producing a multi-layer capacitor

US9691550B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9691550-B2
Application numberUS-201314441467-A
CountryUS
Kind codeB2
Filing dateOct 7, 2013
Priority dateNov 15, 2012
Publication dateJun 27, 2017
Grant dateJun 27, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multi-layer capacitor has dielectric layers and electrode layers arranged therebetween. The multi-layer capacitor has a number of segments that are connected to one another. At least one relief region is provided between the segments. The invention furthermore provides a method for producing such a multi-layer capacitor.

First claim

Opening claim text (preview).

The invention claimed is: 1. A multi-layer capacitor comprising: a plurality of dielectric layers; a plurality of electrode layers, wherein the dielectric layers and electrode layers are arranged between each other, the dielectric and electrode layers being arranged so that the multi-layer capacitor comprises a plurality of segments that are connected to one another, wherein at least one connection region is located between the segments, and wherein the segments are strongly connected with each other in the at least one connection region; and a relief region disposed between the segments, wherein the relief region and the at least one connection region are located at the same height relative to a stacking direction of the dielectric and electrode layers, wherein the relief region is at least partially located in an inactive zone and the at least one connection region is at least partially located in an active zone of the multi-layer capacitor, and wherein the segments are not connected to each other or weakly connected to each other in the relief region compared to a connection of the dielectric and electrode layers within the segments. 2. The multi-layer capacitor according to claim 1 , further comprising a first external contact and a second external contact, wherein the plurality of electrode layers comprises a first electrode layer that is electrically connected to the first external contact, and wherein the plurality of electrode layers comprises a second electrode layer that is electrically connected to the second external contact. 3. The multi-layer capacitor according to claim 2 , wherein the plurality of electrode layers further comprises a third electrode layer that is not contact-connected by any external contact. 4. The multi-layer capacitor according to claim 3 , wherein the third electrode layer overlaps with the first electrode layer and the second electrode layer. 5. The multi-layer capacitor according to claim 4 , wherein the relief region is arranged at least partially in a region in which the third electrode layer overlaps neither with the first electrode layer nor with the second electrode layer. 6. The multi-layer capacitor according claim 2 , wherein the relief region extends at least partially into a region in which the first electrode layer and the second electrode layer overlap. 7. The multi-layer capacitor according to claim 1 , wherein three relief regions are disposed between the segments. 8. The multi-layer capacitor according to claim 1 , further comprising external contacts for contact-connecting ones of the electrode layers, wherein the relief region does not adjoin any external contact. 9. The multi-layer capacitor according to claim 1 , wherein the relief region is arranged in a plane parallel to the electrode layers at least in all regions that adjoin outer edges of the multi-layer capacitor. 10. The multi-layer capacitor according to claim 1 , wherein the multi-layer capacitor has a monolithic form. 11. The multi-layer capacitor according to claim 1 , wherein the relief region comprises a gap between the segments. 12. The multi-layer capacitor according to claim 1 , wherein the dielectric layers comprise an anti-ferroelectric material. 13. The multi-layer capacitor according to claim 12 , wherein the dielectric layers comprise lead lanthanum zirconium titanate. 14. The multi-layer capacitor of claim 1 , wherein the at least one connection region is located entirely in an interior of a base body formed by the dielectric and electrode layers, such that the at least one connection region does not extend to an outer side of the base body. 15. A method for producing a multi-layer capacitor, the method comprising: forming a plurality of dielectric layers; forming a plurality of electrode layers, wherein the dielectric layers and the electrode layers are arranged between each other, the dielectric and electrode layers being arranged so that the multi-layer capacitor comprises a plurality of segments that are connected to one another, wherein at least one connection region is located between the segments, and wherein the segments are strongly connected with each other in the at least one connection region; and forming a relief region disposed between the segments, wherein the relief region and the at least one connection region are located at the same height relative to a stacking direction of the dielectric and electrode layers, wherein the relief region is at least partially located in an inactive zone and the at least one connection region is at least partially located in an active zone of the multi-layer capacitor, and wherein the segments are not connected to each other or weakly connected to each other in the relief region compared to a connection of the dielectric and electrode layers within the segments. 16. The method according to claim 15 , wherein forming the dielectric layers and forming the relief region comprise: providing green sheets for forming the dielectric layers; applying a paste comprising an organic material to at least one of the green sheets; arranging the green sheets to form a stack; and sintering the stack. 17. The method according to claim 16 , wherein the paste is applied in such a manner that the dielectric layers are prevented from completely or partially sintering together at points at which the paste is applied. 18. The method according to claim 16 , wherein forming the electrode layers comprises applying a second paste to other ones of the green sheets.

Assignees

Inventors

Classifications

  • characterised in that the layers are not bonded on the totality of their surfaces · CPC title

  • containing also titanates · CPC title

  • Di-electric · CPC title

  • comprising metal as the main or only constituent of a layer, {which is} next to another layer of {the same or of} a {different material (next to a bituminous or tarry layer B32B11/08; next to a water-setting substance layer B32B13/06; next to a glass layer B32B17/061; next to a cellulosic plastic layer B32B23/042)} · CPC title

  • involving the assembly of discrete sheets or panels only · CPC title

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What does patent US9691550B2 cover?
A multi-layer capacitor has dielectric layers and electrode layers arranged therebetween. The multi-layer capacitor has a number of segments that are connected to one another. At least one relief region is provided between the segments. The invention furthermore provides a method for producing such a multi-layer capacitor.
Who is the assignee on this patent?
Epcos Ag
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 27 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).