Semiconductor memory device including shorted variable resistor element of memory cell

Patent metadata

Field	Value
Publication number	US-9691459-B2
Application number	US-201615249845-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Sep 2, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of resistive memory cells arranged in rows and columns, each of the plurality of resistive memory cells comprising a cell transistor and a variable resistor element;
a first memory cell array comprising a first cell transistor connected to one of a plurality of word lines respectively corresponding to the rows and a first variable resistor element connected to one of a plurality of first bit lines respectively corresponding to the columns;
a second memory cell array comprising a second cell transistor connected to one of the plurality of word lines and a second variable resistor element connected to a second bit line corresponding to one of the columns, wherein the second variable resistor element is shorted; and
a reference resistor connected to the second bit line.

2. The semiconductor memory device of claim 1 , further comprising a sense amplifier connected to the one of the plurality of first bit lines and the second bit line.

3. The semiconductor memory device of claim 1 , wherein the second variable resistor element comprises a magnetic tunnel junction (MTJ) element,
wherein the MTJ element is shorted based on a breakdown voltage.

4. The semiconductor memory device of claim 1 , wherein the second variable resistor element is connected in parallel with a conductive via element comprising a conductive material in a via hole.

5. The semiconductor memory device of claim 1 , wherein the reference resistor is included in a reference resistor control circuit,
wherein the reference resistor control circuit comprises:
a plurality of resistors; and
transistors respectively connected in parallel to the plurality of resistors,
wherein the transistors are configured to selectively short the plurality of resistors in response to trimming signals.

6. The semiconductor memory device of claim 5 , wherein the trimming signals are applied during a process of testing the semiconductor memory device.

7. The semiconductor memory device of claim 1 , wherein the resistive memory cells comprise at least one of spin-transfer torque-magnetoresistive random-access memory (STT-MRAM) cells, magnetoresistive random-access memory (MRAM) cells, phase change random-access memory (PRAM) cells, and resistive random-access memory (ReRAM) cells.

8. A semiconductor memory device comprising:
a plurality of resistive memory cells arranged in rows and columns, each of the plurality of resistive memory cells comprising a cell transistor and a variable resistor element;
a first memory cell array comprising a first cell transistor connected to one of a plurality of word lines respectively corresponding to the rows and a first variable resistor element connected to one of a plurality of first bit lines respectively corresponding to the columns;
a second memory cell array comprising a second cell transistor connected to one of the plurality of word lines and a second variable resistor element connected to a second bit line corresponding to one of the columns, wherein the second bit line is connected to a connection node between the second cell transistor and the second variable resistor element; and
a reference resistor connected to the second bit line.

9. The semiconductor memory device of claim 8 , further comprising a sense amplifier connected to the one of the plurality of first bit lines and the second bit line.

10. The semiconductor memory device of claim 8 , wherein the connection node is a pad electrode connected to a drain of the second cell transistor and the second variable resistor element.

11. The semiconductor memory device of claim 8 , wherein the reference resistor has an intermediate resistance value that is between resistance values corresponding to a first data logic and a second data logic stored in the first variable resistor element.

12. A semiconductor memory device comprising:
a main memory cell array comprising first resistive memory cells, the first resistive memory cells respectively comprising a first cell transistor and a first variable resistor element connected between the first cell transistor and a first bit line;
a reference memory cell array comprising second resistive memory cells, the second resistive memory cells respectively comprising a second cell transistor and a second variable resistor element connected between the second cell transistor and a second bit line, wherein the second variable resistor element comprises an electrical short; and
a reference resistor circuit comprising at least one reference resistor coupled to the second bit line.

13. The semiconductor memory device of claim 12 , further comprising:
a sense amplifier coupled to the first and second bit lines and configured to detect and amplify respective currents flowing therein,
wherein a resistance value of the at least one reference resistor coupled to the second bit line is between resistance values corresponding to first and second logic states of the first variable resistor element.

14. The semiconductor memory device of claim 13 , wherein the resistance value of the at least one reference resistor comprises a narrower range than the resistance values corresponding to first and second logic states of the first variable resistor element.

15. The semiconductor memory device of claim 13 , wherein the at least one reference resistor has a fixed resistance.

16. The semiconductor memory device of claim 15 , wherein the at least one reference resistor comprises a plurality of resistors having respective fixed resistances, and wherein the reference resistor circuit comprises:
a plurality of transistors, the transistors connected in parallel to the resistors, respectively,
wherein the transistors are configured to selectively short the resistors in response to respective trimming signals to provide the resistance value that is between the resistance values corresponding to the first and second logic states of the first variable resistor element.

17. The semiconductor memory device of claim 12 , wherein the second variable resistor element comprises a magnetic tunnel junction (MTJ) element having a breakdown voltage associated therewith, and wherein the electrical short is provided by the MTJ element responsive to application of a voltage greater than the breakdown voltage thereto.

18. The semiconductor memory device of claim 12 , wherein the electrical short comprises a conductive via element that extends through a via hole and is electrically connected in parallel with the second variable resistor element.

19. The semiconductor memory device of claim 12 , wherein the electrical short comprises a connection of the second bit line to a connection node between the second cell transistor and the second variable resistor element.

20. The semiconductor memory device of claim 12 , wherein the second variable resistor element comprises a conductive via element that extends through a via hole to provide the electrical short.

Assignees

• Seo Bo-Young
• Pyo Suk-Soo
• Koh Gwan-Hyeob
• Lee Yong-Kyu
• Kim Dae-Shik
• Samsung Electronics Co Ltd

Inventors

• Seo Bo-Young
• Pyo Suk-Soo
• Koh Gwan-Hyeob
• Lee Yong-Kyu
• Kim Dae-Shik

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/165

  Auxiliary circuits · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title