Shift register unit, shift register and display apparatus

Patent metadata

Field	Value
Publication number	US-9691312-B2
Application number	US-201314374297-A
Country	US
Kind code	B2
Filing date	Dec 5, 2013
Priority date	Aug 29, 2013
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A shift register unit, a shift register and a display apparatus are provided. The shift register unit includes a voltage-boosting module configured to output a first level signal when receiving a gate driving signal sent from the previous stage of shift register unit; a signal output module configured to output a gate driving signal under the control of a first clock signal based on the first level signal output by the voltage-boosting module; a reset module configured to control the signal output module to reset under the control of a reset signal; and a pull-down module configured to pull down the output level of the signal output module under the control of a second clock signal. It is possible to reduce the power consumption of the integrated circuit and avoid the abnormal waveform issue due to the decay of the reset signal by employing the technical solutions of embodiments of the present disclosure.

First claim

What is claimed is:

1. A shift register unit, comprising:
a voltage-boosting module configured to output a first level signal when receiving a gate driving signal sent from the previous stage of shift register unit or a start signal;
a signal output module configured to output a gate driving signal under the control of a first clock signal based on the first level signal outputted by the voltage-boosting module;
a reset module configured to control the signal output module to reset under the control of a reset signal;
a pull-down module configured to pull down the output level of the signal output module under the control of a second clock signal; and
a charge-sharing switch configured to connect the output terminal of the current stage of shift register unit to the output terminal of the next stage of shift register unit to perform charge sharing under the control of the reset signal.

2. The shift register unit according to claim 1 , wherein
the voltage-boosting module comprises a first transistor whose gate is connected to a signal input terminal, whose first electrode is connected with the first level signal, and whose second electrode is connected to a first capacitor;
the reset module comprises a second transistor whose gate is connected with the reset signal, whose first electrode is connected to the second electrode of the first transistor, and whose second electrode is connected with the second level signal;
the signal output module comprises a third transistor, a sixth transistor and the capacitor, a first electrode of the third transistor is connected with the first clock signal, the gate of the third transistor is connected to a second electrode of the sixth transistor, a second electrode of the third transistor is connected to a shift register output terminal, the gate of the sixth transistor is connected with the first clock signal, a first electrode of the sixth transistor is connected to a first electrode of the first capacitor, and the second electrode of the sixth transistor is connected to the gate of the third transistor;
the pull-down module comprises a fourth transistor whose gate is connected with the second clock signal, whose first electrode is connected to the shift register output terminal, and whose second electrode is connected with the second level signal; and
the charge-sharing switch comprises a fifth transistor whose gate is connected with the reset signal, whose first electrode is connected to the output terminal of the current stage of shift register unit, and whose second electrode is connected to the output terminal of the next stage of shift register unit.

3. The shift register unit according to claim 2 , wherein
the first level signal is a high level voltage, and the second level signal is a low level voltage.

4. The shift register unit according to claim 3 , wherein
when the voltage-boosting module receives the gate driving signal from the previous stage of shift register unit or the start signal, the first level signal is output to the signal output module;
the output terminal receives the charges shared with the previous stage of shift register unit;
the signal output module outputs the gate driving signal under the control of the first clock signal after receiving the first level signal;
the charge-sharing switch shares the output gate driving signal with the output terminal of the next stage of shift register unit under the control of the reset signal;
the reset module controls the signal output module to reset under the control of the reset signal, and the pull-down module pulls down the output level of the signal output module under the control of the second clock signal.

5. A shift register comprising multiple stages of cascaded shift register units according to claim 1 , wherein
the signal input terminal of each stage of shift register unit other than the first stage is connected to the signal output terminal of the previous stage of shift register unit; and
the reset module and the charge-sharing switch of each stage of shift register unit are connected with a reset signal, wherein the odd stages of shift register unit is connected with a first reset signal, and the even stages of shift register unit is connected with a second reset signal.

6. A display apparatus comprising the shift register according to claim 5 .

7. The shift register according to claim 5 , wherein
the voltage-boosting module comprises a first transistor whose gate is connected to a signal input terminal, whose first electrode is connected with the first level signal, and whose second electrode is connected to a first capacitor;
the reset module comprises a second transistor whose gate is connected with the reset signal, whose first electrode is connected to the second electrode of the first transistor, and whose second electrode is connected with the second level signal;
the signal output module comprises a third transistor, a sixth transistor and the capacitor, a first electrode of the third transistor is connected with the first clock signal, the gate of the third transistor is connected to a second electrode of the sixth transistor, a second electrode of the third transistor is connected to a shift register output terminal, the gate of the sixth transistor is connected with the first clock signal, a first electrode of the sixth transistor is connected to a first electrode of the first capacitor, and the second electrode of the sixth transistor is connected to the gate of the third transistor;
the pull-down module comprises a fourth transistor whose gate is connected with the second clock signal, whose first electrode is connected to the shift register output terminal, and whose second electrode is connected with the second level signal; and
the charge-sharing switch comprises a fifth transistor whose gate is connected with the reset signal, whose first electrode is connected to the output terminal of the current stage of shift register unit, and whose second electrode is connected to the output terminal of the next stage of shift register unit.

8. The shift register unit according to claim 7 , wherein
the first level signal is a high level voltage, and the second level signal is a low level voltage.

9. The shift register unit according to claim 8 , wherein
when the voltage-boosting module receives the gate driving signal from the previous stage of shift register unit or the start signal, the first level signal is output to the signal output module;
the output terminal receives the charges shared with the previous stage of shift register unit;
the signal output module outputs the gate driving signal under the control of the first clock signal after receiving the first level signal;
the charge-sharing switch shares the output gate driving signal with the output terminal of the next stage of shift register unit under the control of the reset signal;
the reset module controls the signal output module to reset under the control of the reset signal, and the pull-down module pulls down the output level of the signal output module under the control of the second clock signal.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Zhiyong
• Yu Yao
• Xu Shuai
• Zhang Zhengxin
• Zheng Yi

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title