Semiconductor device for performing test and repair operations

Patent metadata

Field	Value
Publication number	US-9690723-B2
Application number	US-201414253971-A
Country	US
Kind code	B2
Filing date	Apr 16, 2014
Priority date	Apr 22, 2013
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

First claim

What is claimed is:

1. A semiconductor device comprising:
a storage unit configured to store program codes provided through control of a processor core; and
a control unit configured to perform a control operation on a semiconductor memory device according to the program codes,
wherein the control unit comprises:
a function decoder configured to analyze a function to be performed on the semiconductor memory device from the program codes;
a code controller configured to control a processing order of the program codes according to a control of the function decoder;
a command generator configured to generate a command to be provided to the semiconductor memory device from the program codes; and
an address generator configured to generate an address to be provided to the semiconductor memory device.

2. The semiconductor device of claim 1 , wherein addresses of a different area from the semiconductor memory device are allocated to the storage unit.

3. The semiconductor device of claim 1 , wherein the storage unit comprises:
a first area for storing the program codes;
a second area for storing data used in the program codes; and
a third area for storing data read from the semiconductor memory device.

4. The semiconductor device of claim 1 , wherein the program code comprises:
a first code indicating a start or an end of the control operation on the semiconductor memory device; and
a second code indicating specific contents of the control operation.

5. The semiconductor device of claim 1 , wherein the control unit further comprises:
a data input/output unit configured to generate first data to be written to the semiconductor memory device or store second data read from the semiconductor memory device according to the control of the function decoder.

6. The semiconductor device of claim 5 , wherein the data input/output unit provides the second data to the storage unit.

7. The semiconductor device of claim 1 , wherein the control unit further comprises:
a delay controller configured to delay an operation of the code controller according to the control of the function decoder.

8. The semiconductor device of claim 1 , wherein the control unit further comprises:
a buffer configured to temporarily store a program code read from the storage unit.

9. A semiconductor device comprising:
a storage unit configured to store program codes provided through control of a processor core;
a first control unit configured to control a semiconductor memory device according to the program codes; and
a second control unit configured to control the semiconductor memory device to process a request from the processor core,
wherein the first control unit comprises:
a function decoder configured to analyze a function to be performed on the semiconductor memory device from the program codes;
a code controller configured to control a processing order of the program codes according to control of the function decoder;
a command generator configured to generate a command to be provided to the semiconductor memory device from the program codes;
an address generator configured to generate an address to be provided to the semiconductor memory device; and
a data input/output unit configured to generate first data to be written to the semiconductor memory device or store second data read from the semiconductor memory device according to the control of the function decoder.

10. The semiconductor device of claim 9 , wherein addresses of a different area from the semiconductor memory device are allocated to the storage unit.

11. The semiconductor device of claim 9 , further comprising:
a first bus commonly interfaced to the storage unit and the second control unit to electrically couple the storage unit and the second control unit to the processor core.

12. The semiconductor device of claim 11 , further comprising:
a second bus commonly interfaced to the first control unit and the second control unit to electrically couple the first control unit and the second control unit to the semiconductor memory device.

13. The semiconductor device of claim 9 , further comprising:
a first selection unit configured to selectively electrically couple the storage unit or the second control unit to the processor core according to the control of the processor core.

14. The semiconductor device of claim 13 , further comprising:
a second selection unit configured to selectively electrically couple the first control unit or the second control unit to the semiconductor memory device according to control of the first control unit.

15. The semiconductor device of claim 9 , wherein the storage unit comprises:
a first area for storing the program codes;
a second area for storing data used in the program codes; and
a third area for storing data read from the semiconductor memory device.

16. The semiconductor device of claim 9 , wherein the first control unit further comprises:
a delay controller configured to delay the operation of the code controller according to the control of the function decoder.

17. The semiconductor device of claim 9 , wherein the first control unit is configured to read and to analyze a series of the program codes to determine an operation to be performed by the semiconductor memory device.

Assignees

• Sk Hynix Inc

Inventors

• Yang Hyung-Gyun
• Lee Hyung-Dong
• Kwon Yong-Kee
• Moon Young-Suk
• Kim Hong-Sik

Classifications

• G06F13/1673 Primary

  using buffers · CPC title

• G06F13/30

  with priority control · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title