Mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof

Patent metadata

Field	Value
Publication number	US-9690719-B2
Application number	US-201414483273-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Sep 11, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. The mechanism comprises at least one context register and a bus interface for receiving a request. A filtering unit obtains information relating to a context of the received request. If in the available state, a managing unit loads the context register with the obtained context information; and grants access in response to the received request. If in the locked state, the managing unit detects whether the obtained context information matches with the context information stored in the context register; and if the obtained and stored context information match, grants access in response to the received request. Otherwise, access is denied.

First claim

What is claimed is:

1. A shared integrated peripheral of a processing unit, the shared integrated peripheral comprising a mechanism for managing access to the shared integrated peripheral, wherein the mechanism is operative in one of at least two operational states comprising an available state and a locked state, wherein the mechanism comprises:
at least one context register for storing context information;
a lock status register;
a bus interface for receiving a request communicated via a bus to the integrated peripheral of the processing device;
a managing unit; and
a filtering unit operably inter-coupled between the bus interface and one or more circuitries of the integrated peripheral and further operably coupled to the managing unit, wherein the filtering unit is arranged to
obtain context information relating to a context of the received request;
wherein the managing unit is arranged to
if the operative state of the mechanism is in the available state as indicated by the lock status register:
load the context register with the obtained context information, and
grant access in response to the received request; and

if the operative state of the mechanism is in the locked state as indicated by the lock status register:
detect whether the obtained context information matches with the context information stored in the context register; and
if the obtained and stored context information match, grant access in response to the received request.

2. The shared integrated peripheral of claim 1 , wherein the request is one of at least an access request, a lock request and a release request;
wherein the managing unit is further arranged to
cause a transition of the operative state from the available state to the locked state in case of granted access in response to the received request being one of a first access request or a lock request; and
cause a transition of the operative state from the locked state to the available state in case of granted access in response to the received request being a release request.

3. The shared integrated peripheral of claim 1 , wherein the received request is a release request, in accordance with which the managing unit is arranged to clear the context register upon granted access.

4. The shared integrated peripheral of claim 1 , wherein the managing unit is arranged to
discard the received request in case the obtained and stored context information do not match.

5. The shared integrated peripheral of claim 4 , wherein the managing unit is arranged to
issue a notification in case the obtained and stored context information do not match.

6. The shared integrated peripheral of claim 1 , wherein the received request is an access request,
wherein the filtering unit is further arranged to
forward the received request to one or more circuitries of the integrated peripheral to be processed thereat in case of granted access.

7. The shared integrated peripheral of claim 1 , further comprising:
a timer operably coupled to the managing unit,
wherein the managing unit is further arranged to
reset the timer in response to granting the received request.

8. The shared integrated peripheral of claim 7 , wherein the timer is further arranged to
issue a signal to the managing unit upon elapsing of a predefined period of time;
wherein the managing unit is further arranged to
clear the context register upon receiving the signal.

9. The shared integrated peripheral of claim 1 ,
wherein the mechanism is in available state in case the context register is cleared; and
wherein the mechanism is in locked state in case the context register is loaded with context information.

10. The shared integrated peripheral of claim 1 , further comprising:
at least one state register for storing the operational state of the mechanism, wherein the state register is readable via the bus interface.

11. A method of operating a mechanism for managing access to a shared integrated peripheral of a processing unit, wherein the mechanism is located in the shared integrated peripheral and is operative in one of at least two operation states comprising an available state and a locked state, wherein the method comprises:
receiving a request communicated via a bus to the integrated peripheral of the processing device,
obtaining information relating to a context of the received request;
if the operative state of the mechanism is in the available state as indicated by a lock status register of the mechanism,
loading a context register for storing context information with the obtained context information, wherein the operative state of the mechanism transitions from the available state to the locked state; and
granting access in response to the received request; and

if the operative state of the mechanism is in the locked state as indicated by the lock status register of the mechanism,
detecting whether the obtained context information matches with the context information stored in the context register; and
if the obtained and stored context information match, granting access in response to the received request.

12. The method of claim 11 , wherein the request is one of at least an access request, a lock request and a release request, the method further comprising:
transitioning of the operative state from the available state to the locked state in case of granted access in response to the received request being one of a first access request or a lock request; and
transitioning of the operative state from the locked state to the available state in case of granted access in response to the received request being a release request.

13. The method of claim 11 , further comprising:
clearing the context register upon granted access if the received request is a release request.

14. The method of claim 11 , further comprising:
discarding the received request in case the obtained and stored context information do not match.

15. The method of claim 11 , further comprising:
forwarding the received request to one or more circuitries of the integrated peripheral to be processed thereat in case of granted access if the received request is an access request.

16. The method of claim 11 , further comprising:
resetting a timer to a predefined period of time in response to granting the received request.

17. The method of claim 16 , further comprising:
generating a signal upon elapsing of a predefined period of time as indicated by the timer; and
clearing the context register upon receiving of the signal.

18. A system comprising a hardware status manager for managing access to a first shared peripheral and for managing access to a second shared peripheral, the first shared peripheral, the first shared peripheral and the hardware status manager connected to a bus connected to a processor, the hardware status manager comprising a first lock status register and a first context register corresponding to the first shared peripheral, and a second lock status register and a second context register corresponding to the second shared peripheral, wherein in response to receiving a first request directed to the first shared peripheral and associated with first context information,
if an operative state of the first shared peripheral is in an available state as indicated by the first lock status register:
load the first context register with the first context information, and
grant access in response to the first request; and

if the operative state of the first shared peripheral is in the locked state as indicated by the loc

Assignees

• Steinert Frank
• Kovalev Andrey
• Nxp Usa Inc

Inventors

• Steinert Frank
• Kovalev Andrey

Classifications

• G06F13/1642 Primary

  with request queuing · CPC title

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/5022

  Mechanisms to release resources · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title