System and method for updating firmware in real-time

Patent metadata

Field	Value
Publication number	US-9690572-B2
Application number	US-201614989767-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jul 17, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A system controlled by firmware includes a memory and a processor. The memory includes a first memory block for storing non-programmable code used for performing key functions, and second and third memory blocks for storing programmable code used for performing normal functions. During operation, one of the second and third memory blocks in which the programmable code is being executed is an active memory block. After receiving new programmable code, the processor identifies the inactive memory block, stores the new programmable code therein, and switches to execute the new programmable code while continuing to perform the key functions using the non-programmable code.

First claim

The invention claimed is:

1. A system controlled by a firmware, wherein the firmware comprises a set of non-programmable code to perform at least one key function and a set of programmable code to perform at least one normal function, the system comprising:
a memory including:
a first memory block that stores the set of non-programmable code of the firmware,
a second and third memory blocks that include an active memory block and an inactive memory block, wherein the active memory block stores a first set of programmable code of the firmware that is currently being executed by the system and the inactive memory block stores a second set of programmable code of the firmware that is not currently being executed by the system, and
a fourth memory block that stores firmware data, wherein the firmware data comprises a set of non-programmable data corresponding to the set of non-programmable code of the firmware and a set of programmable data corresponding to the set of programmable code of the firmware being executed by the system; and

a processor, connected to the memory, comprising:
an input unit that receives a new set of programmable code of the firmware and a firmware updating request,
a processing unit, connected to the input unit, that executes the set of non-programmable code of the firmware stored in the first memory block and the first set of programmable code of the firmware stored in the active memory block, and
a programming unit, connected to the input unit, that identifies the inactive memory block and stores the new set of programmable code of the firmware in the inactive memory block based on said identifying,
wherein after said storing the new set of programmable code of the firmware in the inactive memory block based on said identifying, the processing unit switches from executing the first set of programmable code of the firmware stored in the active memory block to executing the new set of programmable code of the firmware stored in the inactive memory block based on the firmware updating request, and
wherein the system continues to perform the at least one key function during said storing and switching steps.

2. The system of claim 1 , wherein said storing includes removing the second set of programmable code of the firmware stored in the inactive memory block.

3. The system of claim 1 , wherein the input unit comprises a buffer that buffers a portion of the new set of programmable code of the firmware, and wherein the programming unit stores the portion of the new set of programmable code of the firmware in the inactive memory block after a predefined amount of the portion of the new set of programmable code of the firmware is received in the buffer.

4. The system of claim 1 , wherein one of the second and third memory blocks is configured as a default memory block, wherein the processing unit switches to execute the set of programmable code of the firmware in the default memory block if the processing unit fails to identify the active memory block.

5. The system of claim 4 , further comprising a first register that stores a first flag that indicates the active memory block and a second register that stores a second flag that indicates the default memory block, wherein the processor further comprises a control unit, connected to the input unit and the processing unit, that sets the first and second flags, wherein the active and inactive memory blocks are identified based on the first flag, and wherein the default memory block is identified based on the second flag.

6. The system of claim 5 , wherein the firmware updating request comprises a real-time firmware updating request and a non-real-time firmware updating request, wherein the system further comprises a third register that stores a third flag that indicates the firmware updating request is the real-time firmware updating request or the non-real-time firmware updating request, and wherein the control unit sets the third flag upon receipt of the firmware updating request.

7. The system of claim 6 , wherein the processing unit disables all maskable interrupts except interrupts used in the non-programmable code of the firmware during said switching if the third flag indicates the real-time firmware updating request, and disables all maskable interrupts during said switching if the third flag indicates the non-real-time firmware updating request.

8. The system of claim 6 , wherein the processing unit initializes the system except the non-programmable code of the firmware during said switching if the third flag indicates the real-time firmware updating request, and initializes the system during said switching if the third flag indicates the non-real-time firmware updating request.

9. The system of claim 1 , wherein the memory further comprises a first sub-memory unit including the second memory block, a second sub-memory unit including the first and third memory blocks, and a third sub-memory unit including the fourth memory block and a reserved memory block that stores a copy of the set of non-programmable code of the firmware when the programming unit is storing the new set of programmable code of the firmware in the third memory block of the second sub-memory unit or the second memory block of the first sub-memory unit.

10. The system of claim 1 , wherein the memory further comprises a first sub-memory unit including the first, second, and third memory blocks, and a second sub-memory unit including the fourth memory block and a reserved memory block that stores a copy of the set of non-programmable code of the firmware when the programming unit is storing the new set of programmable code of the firmware into one of the second and third memory blocks of the first sub-memory unit.

11. The system of claim 1 , wherein the memory further comprises a plurality of sub-memory units, wherein the second and third memory blocks are located in two separate sub-memory units of the memory respectively, and the first set of programmable code of the firmware and the second set of programmable code of the firmware are respectively stored in the two separate sub-memory units of the memory from a same address, and wherein said switching includes swapping the two separate sub-memory units of the memory with each other.

12. A method of updating firmware of a firmware controlled system, wherein the firmware includes a set of non-programmable code to perform at least one key function and a set of programmable code to perform at least one normal function, and wherein the firmware controlled system comprises a memory including a first memory block that stores the set of non-programmable code of the firmware, a second and third memory blocks that include an active memory block storing a first set of programmable code of the firmware that is currently being executed by the firmware controlled system and an inactive memory block storing a second set of programmable code of the firmware that is not currently being executed by the firmware controlled system, and a fourth memory block that stores firmware data, wherein the firmware data comprises a set of non-programmable data corresponding to the set of non-programmable code of the firmware and a set of programmable data corresponding to the set of programmable code of the firmware being executed by the system, the method comprising:
receiving a new set of programmable code of the firmware and a firmware updating request;
executing the set of non-programmable code of the firmware stored in the first memory block and the first set of programmable code of the firmware stored in the active memory block;
identifying the inactive memory block;
storing the new set of programmable code of the f

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Ye Wanfu
• Zhou Xuwei

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0614

  Improving the reliability of storage systems · CPC title

• G06F8/67 Primary

  Physics · mapped topic

• G06F3/064

  Management of blocks · CPC title

• G06F8/656 Primary

  while running · CPC title