Auto-vectorization in just-in-time compilers for dynamically typed programming languages

Patent metadata

Field	Value
Publication number	US-9690551-B2
Application number	US-201615083157-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Apr 7, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A computing device with an optimizing compiler is disclosed that is configured to generate optimized machine code including a vector operation corresponding to multiple scalar operations where the vector operation is a single operation on multiple pairs of operands. The optimizing compiler includes a vector guard condition generator configured to generate a vector guard condition for one or more vector operations, a mapping module to generate a mapping between elements of the vector guard condition and positions of the relevant scalar operations in the non-optimized machine code or intermediate representation of the source code, and a guard condition handler configured to initiate execution from a particular scalar operation in the non-optimized machine code or intermediate representation if the vector guard condition is triggered. The computing device may include a non-optimizing compiler and/or an interpreter to perform execution of the scalar operations if the vector guard condition is triggered.

First claim

What is claimed is:

1. A method for compiling source code, the method comprising:
receiving source code of a dynamically-typed language wherein types of operations are not defined in the source code;
generating an intermediate representation of the source code;
creating and executing non-optimized machine code that includes multiple scalar operations;
determining if the multiple scalar operations are frequently executed so that the non-optimized machine code may be optimized;
transforming, if the non-optimized machine code may be optimized, the multiple scalar operations in the intermediate representation from a scalar form to a vector operation, wherein each scalar operation includes a single pair of operands, and the vector operation is single operation on multiple pairs of operands;
creating a vector guard condition for, at least, the vector operation;
creating optimized machine code that includes the vector operation and the vector guard condition;
executing the optimized machine code containing the vector operation;
mapping an element of the vector guard condition in the optimized machine code to a particular scalar operation of the non-optimized machine code if the vector guard condition is triggered during execution of the vector operation in the optimized machine code; and
executing the non-optimized code from the particular scalar operation if the optimized machine code fails the vector guard condition.

2. The method of claim 1 , including:
comparing a reference vector with an output of the vector operation to determine if the vector guard condition is triggered.

3. The method of claim 1 , including switching to execute the optimized machine code after executing the non-optimized machine code.

4. The method of claim 1 , wherein mapping includes
generating a mapping table that maps, for the vector guard condition, each of a plurality of element positions of the vector operation to a node in the non-optimized machine code.

5. A non-transitory, tangible processor readable storage medium, encoded with processor readable instructions to perform a method for compiling source code, the method comprising:
receiving source code of a dynamically-typed language wherein types of operations are not defined in the source code;
generating an intermediate representation of the source code;
creating and executing non-optimized machine code that includes multiple scalar operations;
determining if the multiple scalar operations are frequently executed so that the non-optimized machine code may be optimized;
transforming, if the non-optimized machine code may be optimized, the multiple scalar operations in the intermediate representation from a scalar form to a vector operation, wherein each scalar operation includes a single pair of operands, and the vector operation is single operation on multiple pairs of operands;
creating a vector guard condition for, at least, the vector operation;
creating optimized machine code that includes the vector operation and the vector guard condition;
executing the optimized machine code containing the vector operation;
mapping an element of the vector guard condition in the optimized machine code to a particular scalar operation of the non-optimized machine code if the vector guard condition is triggered during execution of the vector operation in the optimized machine code; and
executing the non-optimized code from the particular scalar operation if the optimized machine code fails the vector guard condition.

6. The non-transitory, tangible processor readable storage medium of claim 5 , including:
comparing a reference vector with an output of the vector operation to determine if the vector guard condition is triggered.

7. The non-transitory, tangible processor readable storage medium of claim 5 , including switching to execute the optimized machine code after executing the non-optimized machine code.

8. The non-transitory, tangible processor readable storage medium of claim 5 , wherein mapping includes
generating a mapping table that maps, for the vector guard condition, each of a plurality of element positions of the vector operation to a node in the non-optimized machine code.

Assignees

• Qualcomm Innovation Ct Inc

Inventors

• De Subrato K
• Ahmad Zaheer
• Sule Dineel D
• Ding Yang

Classifications

• G06F9/45529

  Embedded in an application, e.g. JavaScript in a Web browser · CPC title

• G06F8/41 Primary

  Compilation · CPC title

• G06F9/45504

  Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators · CPC title

• G06F8/453

  Data distribution · CPC title