Asynchronously clearing page frames

Patent metadata

Field	Value
Publication number	US-9690483-B2
Application number	US-201715399087-A
Country	US
Kind code	B2
Filing date	Jan 5, 2017
Priority date	Sep 29, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.

First claim

What is claimed is:

1. A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions comprising:
receiving from a first processor a first request for a frame for use in backing a virtual memory page of a unit of work;
producing one or more clean frames for use in backing virtual memory pages, the producing the one or more clean frames comprising clearing a batch of one or more frames selected from a to-clear queue, and the producing the one or more clean frames being performed asynchronously from the unit of work being performed by the first processor;
adding the one or more clean frames to a clean frame queue, the clean frame queue comprising a plurality of clean frames that have been cleared;
adding one or more used frames to a standard frame queue, the one or more used frames having not yet been cleared, wherein the standard frame queue is distinct from the clean frame queue and distinct from the to-clear queue;
removing a clean frame, of the one or more clean frames, from the clean frame queue, responsive to the first request, wherein the removing the clean frame from the clean frame queue comprises:
attempting to remove the clean frame from the clean frame queue through a non-constrained transaction on transactional memory, using a transactional memory facility, absent obtaining a spin lock to access the clean frame queue;
determining that the non-constrained transaction failed; and
performing the removing the clean frame from the clean frame queue through a constrained transaction on the transactional memory, responsive to determining that the non-constrained transaction failed, wherein the performing the removing comprises obtaining the spin lock to access the clean frame queue;
delivering the clean frame to the first processor, responsive to the first request;
receiving a second request for a frame;
determining that the transactional memory facility is unavailable for fulfilling the second request; and
removing a used frame from the standard frame queue, responsive to determining that the transactional memory facility is unavailable.

Assignees

• IBM

Inventors

• Miller Jr Robert
• Partlow Steven M
• Rankin Thomas F
• Tuttle Scott B
• Tzortzatos Elpida

Classifications

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F12/08 Primary

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title