Mirror array in digital pattern generator (DPG)

Patent metadata

Field	Value
Publication number	US-9690208-B2
Application number	US-201314102309-A
Country	US
Kind code	B2
Filing date	Dec 10, 2013
Priority date	Dec 10, 2013
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

Systems and method directed to digital pattern generator (DPG) having a mirror array in an e-beam lithography system are discussed. The mirror array includes a first bank of mirrors and a second bank of mirrors with a combination logic structure interposing the first and second banks of mirrors. An output data line extends from the first bank of mirrors to the combinational logic structure. An input data line that carries data associated with the second bank of mirrors is also provided to the combinational logic structure. An output data line extends from the combinational logic structure to second data bank.

First claim

What is claimed is:

1. An electron-beam lithography system, comprising:
a digital pattern generator (DPG) having a mirror array, wherein the mirror array includes: a first bank of mirrors and a second bank of mirrors;
a combinational logic structure interposing the first and second banks of mirrors;
a first output data line from the first bank of mirrors to the combinational logic structure;
an input data line provided to the combinational logic structure, wherein the input data line carries data associated with the second bank of mirrors; and
a second output data line from the combinational logic structure to second data bank.

2. The system of claim 1 , wherein the combinational logic structure is one of a XOR, XNOR, and a multiplexor (MUX).

3. The system of claim 1 , wherein the DPG further comprises: a third output data line from the second bank of mirrors coupled to a built-in-self-test (BIST) structure.

4. The system of claim 3 , wherein the BIST structure is operable to compare data on the third output data line with data on the input data line.

5. The system of claim 1 , further comprising: an electron source operable to provide a beam incident the mirror array; and a substrate stage operable to hold a substrate for receiving the beam after reflection from the mirror array.

6. The system of claim 1 , wherein the input data line for the second bank of mirrors carries data defining a reflectivity of mirrors of the second bank of mirrors.

7. The system of claim 1 , further comprising: a second input line provided directly to the first bank of mirrors.

8. The system of claim 1 , further comprising: a third bank of mirrors disposed such that the first bank of mirrors interposes the third bank of mirrors and the second bank of mirrors; and a second combinational structure interposing the third bank and the first bank.

9. The system of claim 8 , further comprising: a third output data line from the third bank of mirrors to the second combinational structure; and a second input data line directly coupled to the third bank of mirrors.

10. The system of claim 9 , further comprising: a fourth data output line from the second combination structure to the first bank of mirrors.

11. A system, comprising:
a plurality of mirror array banks disposed in a chain, wherein the plurality of mirror array banks has a first mirror array bank at one end and a terminal mirror array bank at an opposing end of the chain;
a combinational logic structure interposing each of the plurality of mirror array banks;
a first input line provided to the first mirror array bank;
a plurality of additional input lines, each additional input line provided to one of the combinational logic structures;
a single output line extending from the terminal mirror array bank; and
a plurality of additional output lines one extending from the first mirror array bank to the adjacent combinational logic structure and one extending from each subsequent mirror array bank prior to the terminal mirror array bank to its adjacent combinational logic structure.

12. The system of claim 11 , further comprising: a built-in-self test (BIST) structure coupled to the mirror array.

13. The system of claim 12 , wherein the single output line is directly connected to the BIST structure.

14. The system of claim 13 , wherein each of the plurality of additional input lines is also provided to the BIST structure.

15. The system of claim 11 , wherein a number of data signals coupled to the mirror array is equal to a number of banks of the mirror array plus one, wherein the data signals includes the first input line, the plurality of additional input lines, and the single output line.

16. An electron-beam lithography system, comprising:
a first bank of mirrors and a second bank of mirrors;
a combinational logic structure interposing the first and second banks of mirrors, wherein the combinational logic structure is one of a XOR, XNOR, and a multiplexor (MUX);
a first output data line from the first bank of mirrors to the combinational logic structure;
an input data line provided to the combinational logic structure, wherein the input data line carries data associated with the second bank of mirrors; and
a second output data line from the combinational logic structure to second data bank.

17. The system of claim 16 , wherein the DPG further comprises:
a third output data line from the second bank of mirrors coupled to a built-in-self-test (BIST) structure operable to compare data on the third output data line with data on the input data line.

18. The system of claim 16 , further comprising:
an electron source operable to provide a beam incident at least one of the two banks of mirrors; and
a substrate stage operable to hold a substrate for receiving the beam after reflection from the bank(s) of mirrors.

19. The system of claim 16 , wherein the input data line for the second bank of mirrors carries data defining a reflectivity of mirrors of the second bank of mirrors.

20. The system of claim 16 , further comprising:
a third bank of mirrors disposed such that the first bank of mirrors interposes the third bank of mirrors and the second bank of mirrors;
a second combinational logic structure interposing the third bank and the first bank;
a third output data line from the third bank of mirrors to the second combinational logic structure; and a
second input data line directly coupled to the third bank of mirrors.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Tsung-Hsin

Classifications

• H01J2237/30405

  Details · CPC title

• H01J2237/31789

  Reflection mask · CPC title

• G03F7/70491 Primary

  Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes · CPC title

• H01J37/3175 Primary

  Projection methods, i.e. transfer substantially complete pattern to substrate · CPC title

• H01J37/3023

  Program control · CPC title