System for display images

Patent metadata

Field	Value
Publication number	US-9690143-B2
Application number	US-201615163851-A
Country	US
Kind code	B2
Filing date	May 25, 2016
Priority date	Jun 29, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A system for displaying images including a display panel is provided. The display panel has a display area and a peripheral area. The display panel includes a metal layer disposed on a first substrate. A second substrate is disposed opposite to the first substrate. A seal is disposed at the peripheral area and between the first and the second substrates and at the peripheral area. A patterned planarization layer is disposed on the first substrate, including an opening and two sidewalls, wherein the opening is located between the two sidewalls and corresponding to the peripheral area. A passivation layer is disposed between the seal and the first substrate, and wherein a portion of the seal is disposed between the two sidewalls of the patterned planarization layer.

First claim

What is claimed is:

1. A system for displaying images, including a display panel having a display area and a peripheral area out of the display area, wherein the display panel comprises:
a first substrate;
a second substrate disposed opposite to the first substrate;
a seal disposed between the first substrate and the second substrate and disposed at the peripheral area;
a patterned planarization layer disposed on the first substrate, comprising an opening and two sidewalls, wherein the opening is located between the two sidewalls and corresponding to the peripheral area; and
a passivation layer disposed between the seal and the first substrate, wherein the passivation layer covers the two sidewalls of the patterned planarization layer;
wherein a portion of the seal is disposed between the two sidewalls of the patterned planarization layer.

2. The system as claimed in claim 1 , wherein a projection area of the opening projecting on the first substrate is 5% to 100% of a projection area of the seal projecting on the first substrate.

3. The system as claimed in claim 2 , wherein the projection area of the opening is greater than 10% of the projection area of the seal.

4. The system as claimed in claim 1 , wherein the opening comprises a plurality of holes.

5. The system as claimed in claim 4 , wherein the plurality of holes are disposed at corners of the peripheral area of the display panel.

6. The system as claimed in claim 1 , wherein a material of the passivation layer comprises silicon nitride or silicon oxide.

7. The system as claimed in claim 1 , further comprising a metal layer disposed between the passivation layer and the first substrate, wherein the passivation layer covers a sidewall of the metal layer.

8. The system as claimed in claim 7 , wherein the passivation layer is disposed between the metal layer and the seal.

9. The system as claimed in claim 7 , further comprising an insulating layer disposed between the metal layer and the first substrate, wherein a portion of the insulating layer is exposed by the opening.

10. The system as claimed in claim 9 , wherein a material of the patterned planarization layer comprises an organic photoresist and a material of the insulating layer comprises silicon nitride or silicon oxide.

11. An electronic device, comprising:
a display, including a display panel having a display area and a peripheral area out of the display area, wherein the display panel comprises:
a first substrate;
a second substrate disposed opposite to the first substrate;
a seal disposed between the first substrate and the second substrate and disposed at the peripheral area;
a patterned planarization layer disposed on the first substrate, comprising an opening and two sidewalls, wherein the opening is located between the two sidewalls and corresponding to the peripheral area; and
a passivation layer disposed between the seal and the first substrate, wherein the passivation layer covers the two sidewalls of the patterned planarization layer;
wherein a portion of the seal is disposed between the two sidewalls of the patterned planarization layer; and
a control unit coupled to the display to provide an input data to the display such that the display displays images.

12. The electronic device as claimed in claim 11 , further comprising a metal layer disposed between the passivation layer and the first substrate, wherein the passivation layer covers a sidewall of the metal layer.

13. The electronic device as claimed in claim 12 , wherein the passivation layer is disposed between the metal layer and the seal.

14. The electronic device as claimed in claim 11 , wherein a projection area of the opening projecting on the first substrate is 5% to 100% of a projection area of the seal projecting on the first substrate.

15. The electronic device as claimed in claim 11 , wherein the opening comprises a plurality of holes.

16. The electronic device as claimed in claim 15 , wherein the plurality of holes are disposed at corners of the peripheral area of the display panel.

17. The electronic device as claimed in claim 11 , wherein a material of the passivation layer comprises silicon nitride or silicon oxide.

18. The electronic device as claimed in claim 11 , further comprising an insulating layer disposed between the passivation layer and the first substrate, wherein a portion of the insulating layer is disposed in the opening.

19. The electronic device as claimed in claim 18 , wherein a material of the patterned planarization layer comprises an organic photoresist and a material of the insulating layer comprises silicon nitride or silicon oxide.

Assignees

• Innocom Technology(Shenzhen) Co Ltd
• Innolux Corp
• Innocom Tech (Shenzhen) Co Ltd

Inventors

• Wang Chun-Ming
• Sung Hsixg-Ju
• Lee Te-Yu

Classifications

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F2202/02

  organic material · CPC title

• G02F1/1339 Primary

  Gaskets; Spacers; Sealing of cells · CPC title

• G02F2001/133357

  Physics · mapped topic

• G02F1/13306

  Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title