Printed circuit board and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9686860-B2
Application number	US-201514831674-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Jul 15, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

First claim

What is claimed is:

1. A printed circuit board comprising:
an insulating layer;
a circuit pattern on the insulating layer; and
a surface treatment layer on the circuit pattern,
wherein the surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern,
wherein the bottom surface of the surface treatment layer comprises:
a first portion contacting with the top surface of the circuit pattern; and
a second portion spaced apart from the insulating layer and the circuit pattern by a predetermined distance,
wherein the width of the top surface of the circuit pattern is narrower than a width of a bottom surface of the circuit pattern, and the bottom surface of the circuit pattern comprises a first area vertically overlapped with the top surface of the circuit pattern and a second area except for the first area,
wherein the second area of the circuit pattern comprises:
a third area that is not vertically overlapped with the second portion of the surface treatment layer; and
a fourth area vertically overlapped with the second portion of the surface treatment layer, and
wherein the third area has a width wider than a width of the fourth area.

2. The printed circuit board of claim 1 , wherein, in the circuit pattern, at least one of an upper right lateral side and an upper left lateral side thereof has a predetermined curvature.

3. The printed circuit board of claim 1 , wherein the width of the third area to the width of the fourth area satisfies a range of 1.5 to 4.0.

4. The printed circuit board of claim 1 , wherein the surface treatment layer comprises a gold (Au) surface treatment layer including a metallic material including gold (Au), and a bottom surface of the gold (Au) surface treatment layer directly makes contact with the top surface of the circuit pattern.

5. The printed circuit board of claim 1 , wherein the bottom surface of the surface treatment layer has a width narrower than the width of the bottom surface of the circuit pattern.

6. The printed circuit board of claim 1 , further comprising a plating seed layer interposed between the insulating layer and the circuit pattern,
wherein the plating seed layer serves as a seed layer for the circuit pattern and the surface treatment layer, and
wherein the second portion of the surface treatment layer is spaced apart from the plating seed layer.

7. The printed circuit board of claim 1 , wherein at least one of a left lateral side and a right lateral side of the circuit pattern comprises a first portion substantially perpendicular to the bottom surface of the circuit pattern and a second portion extending from the first portion and having a curved surface with a predetermined curvature.

8. The printed circuit board of claim 1 , wherein the second portion of the surface treatment layer is floated on the circuit pattern.

9. The printed circuit board of claim 1 , further comprising a protective layer formed on the insulating layer to cover at least a portion of a surface of the insulating layer.

10. A method of fabricating a printed circuit board, the method comprising:
preparing an insulating layer formed on a top surface thereof with a plating seed layer;
forming a circuit pattern on the insulating layer by performing electroplating with respect to the plating seed layer serving as a seed layer;
forming a mask, which has an opening, on the plating seed layer to expose at least a portion of a top surface of the circuit pattern;
forming a surface treatment layer on the circuit pattern by performing electroplating with respect to the plating seed layer serving as the seed layer such that the surface treatment layer is filled in at least a portion of the opening;
removing the mask from the plating seed layer; and
removing the plating seed layer from the insulating layer,
wherein a bottom surface of the surface treatment layer, which exists after the plating seed layer is removed, comprises:
a first portion contacting with the top surface of the circuit pattern; and
a second portion spaced apart from the insulating layer, the plating n seed layer and the circuit pattern by a predetermined distance,
wherein the opening of the mask has a width narrower than a width of the top surface of the circuit pattern, and the at least a portion of the top surface of the circuit pattern is covered by the mask,
wherein the circuit pattern, which exists after the plating seed layer is removed, comprises the top surface having the width narrower than a width of the bottom surface of the surface treatment layer,
wherein a bottom surface of the circuit pattern, which exists after the plating seed layer is removed, comprises a first area vertically overlapped with the top surface of the circuit pattern and a second area except for the first area,
wherein the second area of the circuit pattern comprises:
a third area that is not vertically overlapped with the second portion of the surface treatment layer; and
a fourth area that is vertically overlapped with the second portion of the surface treatment layer, and
wherein the third area has a width wider than a width of the fourth area.

11. The method of claim 10 , wherein the second portion of the surface of the treatment layer is floated on the circuit pattern.

12. The method of claim 10 , wherein the opening of the mask has a width narrower than the width of the top surface of the circuit pattern, and the at least a portion of the top surface of the circuit pattern is covered by the mask.

13. The method of claim 12 , wherein the circuit pattern, which exists before the plating seed layer is removed, comprises a first top surface making contact with the bottom surface of the surface treatment layer and a second top surface that does not make contact with the bottom surface of the surface treatment layer, and a portion of the second top surface of the circuit pattern is removed together with the plating seed layer when the plating seed layer is removed.

14. The method of claim 13 , wherein the circuit pattern, which exists after the plating seed layer is removed, has a lateral side extending from the second top surface and having a predetermined curvature.

15. The method of claim 12 , wherein the surface treatment layer comprises a gold (Au) surface treatment layer including a metallic material including gold (Au), and a bottom surface of the gold (Au) surface treatment layer directly makes contact with the top surface of the circuit pattern.

16. The method of claim 12 , further comprising forming a protective layer on the insulating layer to cover at least a portion of a surface of the insulating layer.

Assignees

• Lg Innotek Co Ltd
• Lg Innotek Co Ltd

Inventors

• Bae Yun Mi
• Kwon Soon Gyu
• Kim Sang Hwa
• Lee Sang Young
• Lee Jin Hak
• Lee Han Su
• Jeong Dong Hun
• Jeong In Ho
• Choi Dae Young
• Hwang Jung Ho

Classifications

• H05K1/0296

  Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18) · CPC title

• C25D3/38

  of copper · CPC title

• H05K2203/1184

  Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching · CPC title

• H05K3/108

  by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241) · CPC title

• H05K3/244 Primary

  Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465) · CPC title