Semiconductor device, ramp signal control method, image data generating method, and camera system

Patent metadata

Field	Value
Publication number	US-9686494-B2
Application number	US-201514753497-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Jul 17, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Conventional semiconductor devices disadvantageously failed to sufficiently enlarge a dynamic range. A semiconductor device according to an embodiment includes a plurality of registers 21 to 26 that sets a gradient of a ramp signal. In the semiconductor device, the values in the registers 24 to 26 that are reflected in the gradient of the ramp signal are switched at predetermined timings, whereby a ramp signal with a gradient that changes at the predetermined timings is generated, and an analog-to-digital converter uses the ramp signal to convert pixel signals acquired from a pixel area into digital values.

First claim

What is claimed is:

1. A semiconductor device comprising:
a pixel area in which charge according to the amount of incident light is accumulated and which outputs pixel signals;
an analog-to-digital converter that reads the pixel signals and outputs digital values each according to the magnitude of a corresponding one of the pixel signals using a ramp signal; and
a ramp signal generating circuit that outputs the ramp signal,
wherein the ramp signal generating circuit includes:
a gradient initialization register that stores an initial gradient setting value indicating a gradient of the ramp signal during an initial gradient period in a preset sweep period;
a first gradient setting register that stores a first gradient setting value indicating the gradient of the ramp signal during a first gradient period following the initial gradient period in the sweep period;
a second gradient setting register that stores a second gradient setting value indicating the gradient of the ramp signal during a second gradient period following the first gradient period in the sweep period;
a first gradient change timing setting register that stores a first change timing value indicating a timing for a change from the initial gradient period to the first gradient period;
a second gradient change timing setting register that stores a second change timing value indicating a timing for a change from the first gradient period to the second gradient period;
a counter that counts reference clocks received during the sweep period and outputs a count value;
a switching control circuit that compares the count value with the first change timing value and compares the count value with the second change timing value to output a select signal;
a selector that outputs one of the initial gradient value, the first gradient setting value, and the second gradient setting value in accordance with the select signal; and
a ramp waveform generating circuit that outputs the ramp signal that changes linearly at a gradient according to the value output by the selector,
wherein the ramp waveform generating circuit comprises:
a current digital-analog conversion circuit that outputs an output current of a magnitude according to the value output by the selector, wherein the current digital-analog conversion circuit comprises a current mirror having a source side transistor connected to a current source and a plurality of branch-side transistors that outputs the output current, and the plurality of branch-side transistors is provided in association with the initial gradient value, the first gradient setting value and the second gradient setting value.

2. The semiconductor device according to claim 1 , wherein the ramp waveform generating circuit comprises:
an integration circuit that integrates the output current to output the ramp signal.

3. The semiconductor device according to claim 2 , wherein
the initial gradient value, the first gradient setting value, and the second gradient setting value are each an n-bit value, and
the current digital-analog conversion circuit varies a current value for the output current in 2n steps within a given range of changes in output current.

4. The semiconductor device according to claim 2 , wherein connection between the source-side transistor and gates of the plurality of branch-side transistors is switched in accordance with the initial gradient value, the first gradient setting value, and the second gradient setting value.

5. The semiconductor device according to claim 2 , wherein the ramp signal generating circuit includes:
an offset setting register that stores an offset setting value for setting a voltage value for an initial ramp signal during the initial gradient period; and
an offset current source that outputs an offset current to the integration circuit in accordance with the offset setting value.

6. The semiconductor device according to claim 2 , wherein the ramp signal generating circuit includes:
an offset setting register that stores a reference voltage setting value for setting a value for a reference voltage provided to the integration circuit; and
a reference voltage generating circuit that varies the reference voltage in accordance with the reference voltage setting value.

7. The semiconductor device according to claim 1 , further comprising a plurality of gradient setting units including the gradient initialization register, the first gradient setting register, the second gradient setting register, the first gradient change timing setting register, the second gradient change timing setting register, and the selector; and
at least one processor configured to execute a setting switching unit that switches an output of one of the plurality of gradient setting units for pixel signals acquired in the pixel area during different exposure times.

8. The semiconductor device according to claim 1 , wherein the first gradient setting value is smaller than the second gradient setting value.

9. A ramp signal control method for a semiconductor device that includes a pixel area in which charge according to the amount of incident light is accumulated and which outputs pixel signals, an analog-to-digital converter that reads the pixel signals and outputs digital values each according to the magnitude of a corresponding one of the pixel signals using a ramp signal, and a ramp signal generating circuit that outputs the ramp signal,
the ramp signal generating circuit including a gradient initialization register, a first gradient setting register, a second gradient setting register, a first gradient change timing setting register, a second gradient change timing setting register, and a ramp waveform generating circuit that outputs the ramp signal that changes linearly, the method comprising:
changing the ramp signal at a gradient according to an initial gradient setting value stored in the gradient initialization register during a period from a beginning of a sweep period in which the ramp signal is changed until a first change timing value stored in the first gradient change timing setting register is reached;
changing the ramp signal at a gradient according to the first gradient setting value stored in the first gradient change timing setting register during a period from the beginning of the sweep period until a second change timing value stored in the second gradient change timing setting register is reached; and
changing the ramp signal at a gradient according to the second gradient setting value stored in the second gradient change timing setting register after a time from the beginning of the sweep period reaches the second change timing value,
wherein the changing the ramp signal includes:
switching a current value by a current mirror having a source side transistor connected to a current source and a plurality of branch-side transistors that outputs an output current, and the plurality of branch-side transistors is provided in association with the initial gradient value, the first gradient setting value and the second gradient setting value.

10. The ramp signal control method according to claim 9 wherein
the ramp waveform generating circuit includes an integration circuit that integrates the output current output by the current source to output the ramp signal.

11. The ramp signal control method according to claim 10 , wherein the initial gradient value, the first gradient setting value, and the second gradient setting value are each a multi-bit value, and the current source varies the current value for the output current in 2n steps within a given range of changes in output current.

12. The ramp signal control method according to claim 9 , wherein th

Assignees

• Renesas Electronics Corp

Inventors

• Aibara Yasutoshi

Classifications

• H03K4/502 Primary

  the capacitor being charged from a constant-current source · CPC title

• H04N23/76

  by influencing the image signals · CPC title

• H04N23/741

  by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/575

  with a response composed of multiple slopes · CPC title