Frequency-domain high-speed bus signal integrity compliance model

Patent metadata

Field	Value
Publication number	US-9686053-B2
Application number	US-201514833643-A
Country	US
Kind code	B2
Filing date	Aug 24, 2015
Priority date	May 26, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Embodiments of the present disclosure provide methods for testing channel compliance. The method generally includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

First claim

What is claimed is:

1. A method for testing channel compliance, comprising:
identifying at least one design criteria; and
determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria, wherein the boundary sets are used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels, wherein the signal channel is part of a communication bus and the bounds sets of frequency domain parameters comprise at least one parameter related to insertion loss and at least one parameter related to a crosstalk ratio at a fundamental frequency of the bus.

2. The method of claim 1 , wherein the boundary sets are determined by using time-domain simulations of S-parameters representing one of a plurality of channel variations, wherein each channel variation is simulated in the time domain by sweeping a plurality of equalization settings.

3. The method of claim 1 , wherein the frequency domain parameters for the particular channel is derived from S-parameters indicative of a frequency response of the particular channel.

4. The method of claim 1 , wherein the design criteria comprises a desired bit error rate for a particular set of bus transmitter and receiver properties.

5. The method of claim 1 , wherein the boundary sets are determined using a genetic algorithm.

6. The method of claim 1 , wherein the particular signal channel is used for communication between a first and second components and the boundary sets are determined for at least one known property of the first and second components.

7. The method of claim 1 , wherein the verifying comprises:
determining whether the particular signal channel is compliant based on a comparison of the frequency domain parameters for the particular channel to frequency domain parameters of a first boundary set; and
if not, determining whether the particular signal channel is compliant based on a comparison of the frequency domain parameters for the particular channel to frequency domain parameters of a second boundary set.

Assignees

• IBM

Inventors

• Becker Wiren D
• Dreps Daniel M
• Hejase Jose A
• Wiedemeier Glen A
• Win Si T

Classifications

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• H04L43/50

  Testing arrangements · CPC title

• H04L1/242 Primary

  by comparing a transmitted test signal with a locally generated replica · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F11/2221

  to test input/output devices or peripheral units · CPC title