Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

Patent metadata

Field	Value
Publication number	US-9685969-B1
Application number	US-201615141498-A
Country	US
Kind code	B1
Filing date	Apr 28, 2016
Priority date	Apr 5, 2016
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) circuit, comprising:
a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal;
first and second DACs each configured to receive respective first and second data streams of the plurality of data streams and to selectively process the respective first and second data streams to generate a respective DAC output signal,
wherein at least one of the first and second DACs is further configured to:
transition from processing a first data value of the respective first data stream to processing a second data value of the respective second data stream in response to a clock transition of a respective clock signal; and
transition from processing a third data value of the respective first data stream to processing a fourth data value of the respective first data stream in response to a data transition of the respective first data stream from the third data value to the fourth data value.

2. The DAC circuit of claim 1 , wherein the clock transition of the respective clock signal includes a rising edge transition or a falling edge transition.

3. The DAC circuit of claim 1 , wherein a rate of the respective clock signal is (n/m) times a data rate of the data signal, where n and m are integers.

4. The DAC circuit of claim 3 , wherein n is lower than m.

5. The DAC circuit of claim 1 , wherein the respective DAC output signal of the first DAC and the respective DAC output signal of the second DAC are coupled to provide an output signal of the DAC circuit.

6. The DAC circuit of claim 5 , wherein an output data value represented by the output signal of the DAC circuit is responsive to the first DAC transitioning from processing the first data value of the respective first data stream to processing the second data value of the respective second data stream and the second DAC transitioning from processing the third data value of the respective first data stream to processing the fourth data value of the respective first data stream.

7. The DAC circuit of claim 6 , wherein the multiplexer/encoder is further configured to encode the data signal to generate the plurality of data streams.

8. The DAC circuit of claim 7 , wherein the multiplexer/encoder is further configured to encode the data signal such that the second data value of the respective second data stream of the first DAC holds an equal value to the fourth data value of the respective first data stream of the second DAC.

9. The DAC circuit of claim 5 , wherein an output data value represented by the output signal of the DAC circuit is responsive to the clock transition of the respective clock signal of the first DAC and the data transition of the respective first data stream of the second DAC.

10. A method for processing data, comprising:
generating a plurality of data streams based on a data signal;
providing, to each of first and second digital-to-analog converters (DACs), respective first and second data streams of the plurality of data streams;
selectively processing the respective first and second data streams to generate a respective DAC output signal by each of the first and second DACs,
wherein selectively processing the respective first and second data streams comprises:
transitioning from processing a first data value of the respective first data stream to processing a second data value of the respective second data stream in response to a clock transition of a respective clock signal; and
transitioning from processing a third data value of the respective first data stream to processing a fourth data value of the respective first data stream in response to a data transition of the respective first data stream from the third data value to the fourth data value.

11. The method of claim 10 , wherein the clock transition of the respective clock signal includes a rising edge transition or a falling edge transition.

12. The method of claim 10 , wherein a rate of the respective clock signal is (n/m) times a data rate of the data signal, where n and m are integers.

13. The method of claim 12 , wherein n is lower than m.

14. The method of claim 10 , further comprising coupling the respective DAC output signal of the first DAC and the respective DAC output signal of the second DAC to provide an output signal.

15. The method of claim 14 , wherein an output data value represented by the output signal is responsive to the first DAC transitioning from processing the first data value of the respective first data stream to processing the second data value of the respective second data stream and the second DAC transitioning from processing the third data value of the respective first data stream to processing the fourth data value of the respective first data stream.

16. The method of claim 15 , further comprising encoding the data signal to generate the plurality of data streams.

17. The method of claim 16 , wherein encoding the data signal comprises encoding the data signal such that the second data value of the respective second data stream of the first DAC holds an equal value to the fourth data value of the respective first data stream of the second DAC.

18. The method of claim 14 , wherein an output data value represented by the output signal is responsive to the clock transition of the respective clock signal of the first DAC and the data transition of the respective first data stream of the second DAC.

19. A method for calibrating a time-interleaved digital-to-analog converter (DAC) circuit, comprising:
applying a training signal to a time-interleaved DAC circuit, the time-interleaved DAC circuit being clocked by a plurality of time-interleaved clock signals;
measuring an output signal of the time-interleaved DAC circuit in response to the training signal;
detecting a spur in the output signal responsive to the measuring; and
adjusting a phase between the time-interleaved clock signals to reduce a magnitude of the detected spur.

20. The method of claim 19 , wherein detecting the spur in the output signal comprises filtering, using a low-pass filter or a band-pass filter, the output signal to isolate the spur.

Assignees

• Avago Technologies General Ip

Inventors

• Garg Adesh
• Nazemi Ali
• Vasani Anand Jitendra
• Rhew Hyo Gyuem
• Zhang Jiawen
• Cao Jun
• Nazari Meisam Honarvar
• Momtaz Afshin
• Ali Tamer

Classifications

• H03M1/10 Primary

  Calibration or testing · CPC title

• H03M1/662 Primary

  Multiplexed conversion systems · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title