Amplification stage and wideband power amplifier

Patent metadata

Field	Value
Publication number	US-9685915-B2
Application number	US-201214439050-A
Country	US
Kind code	B2
Filing date	Oct 31, 2012
Priority date	Oct 31, 2012
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

An amplification stage and a wideband power amplifier are provided. The amplification stage includes a stage input terminal, a stage output terminal, an amplifier, an input compensation network, and in output compensation network. At the stage input terminal is received a signal which is provided via the input compensation network to the amplifier. The input compensation network filters the signal to allow a wideband operation of the amplification stage around an operational frequency. The amplified signal provided by the amplifier is provided via the output compensation network to the stage output terminal. The output compensation network configured to allow a wideband operation of the amplification stage around the operational frequency with a minimal phase shift and distortion of amplitude and phase frequency response. The wideband power amplifier includes a plurality of amplification stage combined with transmission lines or their lumped element equivalents in a specific circuit topology.

First claim

The invention claimed is:

1. An amplification stage for use in a power amplifier and for amplifying a signal in a bandwidth around an operational frequency, the amplification stage comprising:
a stage input terminal for receiving a signal to be amplified;
a stage output terminal for providing an amplified signal;
an amplifier comprising an amplifier input terminal and an amplifier output terminal, the amplifier configured to amplify a signal received at the amplifier input terminal towards a signal provided at the amplifier output terminal;
an input compensation network configured to allow a wideband operation of the amplification stage around the operational frequency, the input compensation network arranged in between the stage input terminal and the amplifier input terminal, the input compensation network comprising a first series arrangement of a first inductor and a first capacitor, the input compensation network further comprising a second inductor and a second capacitor, the first series arrangement coupled between the stage input terminal and the amplifier input terminal, the first series arrangement to transfer the signal received at the stage input terminal with a zero phase shift of the signal, the second inductor coupled between the amplifier input terminal and a first supply voltage terminal coupled to a supply voltage, and the second capacitor coupled between the first supply voltage terminal and a ground voltage; and
an output compensation network configured to allow a wideband operation of the amplification stage around the operational frequency, the output compensation network arranged in between the amplifier output terminal of the amplifier and the stage output terminal, the output compensation network comprising a second series arrangement of a third inductor and a third capacitor, the output compensation network further comprising a fourth inductor and a fourth capacitor, the second series arrangement coupled between the amplifier output terminal and the stage output terminal, the fourth inductor coupled between the amplifier output terminal and a second supply voltage terminal coupled to the supply voltage, and the fourth capacitor coupled between the second supply voltage terminal and a ground voltage.

2. An amplification stage according to claim 1 , wherein
an inductance of the first inductor is substantially equal to L 1 =C gs (Re(Zin)) 2 L 1 ,
a capacitance of the first capacitor is substantially equal to

C
⁢

⁢
1

=

L
2

(

Re
⁡

(

Z
in

)

)

2

,

wherein ω 0 is the operational frequency, V d is the supply voltage, C gs is the parasitic input capacitance of the amplifier, L 2 is the inductance of the second inductor, and Re(Z in ) is real part of an input impedance of the amplifier in the middle of the bandwidth.

3. An amplification stage according to claim 1 , wherein
an inductance of the third inductor is substantially equal to L 1 =C gs (Re(Zin)) 2 ,
a capacitance of the third capacitor is substantially equal to

C
⁢

⁢
3

=

1

4
⁢

ω
0
2

⁢

C
ds

⁢

(

I
d_max

V
d

)

2

,

wherein ω 0 is the operational frequency, V d is the supply voltage, I d _ max is the maximum current to be provided by the amplifier, C ds is the parasitic output capacitance of the amplifier.

4. An amplification stage according to claim 1 , wherein the second inductor is configured to compensate a parasitic input capacitance of the amplifier in the bandwidth around the operational frequency or the fourth inductor is configured to compensate a parasitic output capacitance of the amplifier in the bandwidth around the operational frequency.

5. An amplification stage for use in a power amplifier and for amplifying a signal in a bandwidth around an operational frequency, the amplification stage comprising:
a stage input terminal for receiving a signal to be amplified;
a stage output for providing an amplified signal;
an amplifier comprising an amplifier input terminal and an amplifier output terminal, the amplifier configured to amplify a signal received at the amplifier input terminal towards a signal provided at the amplifier output terminal;
input compensation network configured to allow a wideband operation of the amplification stage around the operational frequency, the input compensation network arranged in between the stage input terminal and the amplifier input terminal, the input compensation network comprising a first series arrangement of a first inductor and a first capacitor, the input compensation network further comprising a second inductor and a second capacitor, the first series arrangement coupled between the stage input terminal and the amplifier input terminal, the second inductor coupled between the amplifier input terminal and a first supply voltage terminal coupled to a supply voltage, and the second capacitor coupled between the first s voltage terminal and a ground voltage; and
an output compensation network configured to allow a wideband operation of the amplification stage around the operational frequency, the output compensation network arranged in between the amplifier output terminal of the amplifier and the stage output terminal, the output compensation network comprising a second series arrangement of a third inductor and a third capacitor, the output compensation network further comprising a fourth inductor and a fourth capacitor, the second series arrangement coupled between the amplifier output terminal and the stage output terminal, the fourth inductor coupled between the amplifier output terminal and a second supply voltage terminal coupled to the supply voltage, and the fourth capacitor coupled between the second supply voltage terminal and a ground voltage, wherein the second

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Blednov Igor

Classifications

• H03F2203/21106

  An input signal being distributed in parallel over the inputs of a plurality of power amplifiers · CPC title

• H03F1/42 Primary

  Modifications of amplifiers to extend the bandwidth · CPC title

• H03F3/604

  using FET's · CPC title

• H03F1/0288 Primary

  using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title

• H03F2203/21142

  Output signals of a plurality of power amplifiers are parallel combined to a common output · CPC title