Charge pump circuit

Patent metadata

Field	Value
Publication number	US-9685856-B2
Application number	US-201615205439-A
Country	US
Kind code	B2
Filing date	Jul 8, 2016
Priority date	Dec 23, 2010
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.

First claim

What is claimed is:

1. A charge pump circuit, comprising:
an input node for connection to an input voltage;
flying capacitor nodes for connecting to flying capacitors;
a first pair of output nodes and a second pair of output nodes;
a switch network for interconnecting said nodes; and
a controller operable to control the switch network to provide first bipolar output voltages at the first pair of output nodes and second bipolar output voltages at the second pair of output nodes;
wherein the switch network comprises at least a first NMOS switch formed on a first region of a semiconductor substrate wherein the first region of the semiconductor substrate is isolated from the rest of the substrate by one or more n-well regions.

2. A charge pump circuit as claimed in claim 1 wherein the one or more n-well regions comprise a deep n-well underlying the first region.

3. A charge pump circuit as claimed in claim 2 wherein the one or more n-well regions comprise a lateral n-well around the periphery of the first region.

4. A charge pump circuit as claimed in claim 1 wherein the first region comprises a p-well region.

5. A charge pump circuit as claimed in claim 1 wherein the first NMOS switch is located in a switching path that is subject, in use, to a negative output voltage.

6. A charge pump circuit as claimed in claim 1 further comprising a second NMOS switch formed on a second region of a semiconductor substrate wherein the second region of the semiconductor substrate is isolated from the rest of the substrate by one or more n-well regions.

7. A charge pump circuit as claimed in claim 6 wherein the first NMOS switch is located in a switching path that is subject, in use, to a negative voltage of the first bipolar output voltage and the second NMOS switch is located in a switching path that is subject, in use, to the negative voltage of the second bipolar output voltage.

8. A charge pump circuit as claimed in claim 6 wherein a single deep n-well underlies both the first and second regions.

9. A charge pump circuit as claimed in claim 1 wherein the controller is configured to control the switch network such that the magnitude of the first bipolar output voltages is selectively variable.

10. A charge pump circuit as claimed in claim 9 wherein the controller is configured to control the switch network such that the magnitude of the second bipolar output voltages is selectively variable.

11. A charge pump circuit as claimed in claim 9 wherein the controller is configured to control the switch network such that the magnitude of the second bipolar output voltages is fixed with respect to the input voltage.

12. A charge pump circuit as claimed in claim 1 comprising wherein the controller is operable to control the switch network to generate the first bipolar output voltage and the second bipolar output voltages in use with only two flying capacitors connected to the flying capacitor nodes.

13. A charge pump circuit as claimed in claim 12 wherein the controller is operable to control the switch network such that the first bipolar output voltage is one of +/−2VV, +/−(3/2)*VV, +/−VV, +/−VV/2, +/−VV/4, or +/−VV/6, where VV is the input supply voltage to the charge pump circuit.

14. A charge pump circuit as claimed in claim 13 wherein the controller is operable to control the switch network such that the second bipolar output voltage is one of +/−VV or +/−VV/2.

15. An audio circuit comprising:
a charge pump circuit as claimed in claim 1 ; and
an amplifier output stage powered, in use, by the first or second bipolar output voltages.

16. An audio circuit as claimed in claim 15 wherein the amplifier output stage comprises a NMOS device formed in a second region of the semiconductor substrate wherein the second region of the semiconductor substrate is isolated from the rest of the substrate by one or more n-well regions.

17. An audio circuit as claimed in claim 16 wherein the amplifier output stage further comprises a PMOS device and the PMOS device is formed in one of said n-well regions isolating the second region of the semiconductor substrate from the rest of the substrate.

18. An electronic device comprising a charge pump circuit as claimed in claim 1 .

19. An apparatus comprising:
a charge pump circuit for generating first and second bipolar output voltages at first and second pairs of output terminals from a unipolar input voltage at an input terminal;
the charge pump circuit comprising a network of switching paths comprising a plurality of switches formed on a semiconductor substrate;
wherein the plurality of switches comprises at least one NMOS switch formed in a p-region isolated from the rest of the semiconductor substrate by one or more n-well regions.

20. A charge pump circuit comprising:
an input terminal for receiving an input voltage;
a first pair of output terminals for outputting a first bipolar output voltage;
a second pair of output terminals for outputting a second first bipolar output voltage; and
a switch network operable in a sequence of switch states so as to generate said first and second bipolar output voltages,
wherein the switch network comprises at least one NMOS switch formed in a region of a semiconductor substrate that is surrounded by one or more n-wells.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Lesso John P
• Frith Peter J
• Pennock John L

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03F3/181

  Low-frequency amplifiers, e.g. audio preamplifiers · CPC title

• H02M2001/0083

  Electricity · mapped topic

• H02M1/00

  Details of apparatus for conversion · CPC title

• H02M2001/009

  Electricity · mapped topic