Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9685462-B2
Application number	US-201514791653-A
Country	US
Kind code	B2
Filing date	Jul 6, 2015
Priority date	Jul 10, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A semiconductor device of an embodiment includes an oxide semiconductor layer including a first region, a second region and the third region provided between the first region and the second region. The oxide semiconductor layer contains indium (In), gallium (Ga), and zinc (Zn). The first and second regions have thinner film thickness and lower indium (In) concentration than the third region. An insulating film is provided on the third region, and an electrode is provided on the insulating film. A first conductive layer is provided under the first region and electrically connected with the first region. A second conductive layer is provided under the second region and electrically connected with the second region.

First claim

What is claimed is:

1. A semiconductor device comprising:
an oxide semiconductor layer including a first region, a second region and a third region provided between the first region and the second region, the oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn), the first and second regions having lower indium (In) concentration than the third region;
an insulating film provided on the third region;
an electrode provided on the insulating film;
a first conductive layer provided under the first region and electrically connected with the first region; and
a second conductive layer provided under the second region and electrically connected with the second region,
wherein
film thickness of the first region directly above an edge of the first conductive layer and film thickness of the second region directly above an edge of the second conductive layer are thinner than film thickness of a middle portion of the third region.

2. The device according to claim 1 , wherein
the film thickness of the third region is 10 nm or more, and the film thickness of the first and the second region is 5 nm or less.

3. The device according to claim 1 , wherein
the oxide semiconductor layer further contains at least one element selected from a group of hafnium (Hf), tin (Sn), aluminum (Al), zirconium (Zr), lithium (Li), scandium (Sc), and nitrogen (N).

4. The device according to claim 1 , wherein
the indium concentration of each of the first and the second regions is 80% or less of the indium concentration of the third region.

5. The device according to claim 1 , further comprising side layers provided at both sides of the electrode.

6. The device according to claim 1 , wherein
the electrode is metal.

7. The device according to claim 1 , wherein
the first conductive layer and the second conductive layer are metal.

8. A semiconductor device comprising:
an oxide semiconductor layer including a first region, a second region and a third region provided between the first region and the second region, the oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn), the first and second regions having thinner film thickness and lower indium (In) concentration than the third region, the film thickness of the third region being 10 nm or more, the film thickness of the first and the second region being 5 nm or less, and the indium concentration of each of the first and the second regions being 80% or less of the indium concentration of the third region;
an insulating film provided on the third region;
an electrode provided on the insulating film;
a first conductive layer provided under the first region and electrically connected with the first region; and
a second conductive layer provided under the second region and electrically connected with the second region.

Assignees

• Toshiba Kk

Inventors

• Ota Kensuke
• Saitoh Masumi
• Sakuma Kiwamu
• Matsushita Daisuke
• Tanaka Chika

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/69

  using masks for semiconductor materials · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title