Cell placement optimization
US-2024371942-A1 · Nov 7, 2024 · US
US9685437B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9685437-B2 |
| Application number | US-201214234364-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 6, 2012 |
| Priority date | Jul 26, 2011 |
| Publication date | Jun 20, 2017 |
| Grant date | Jun 20, 2017 |
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Official abstract text for this publication.
The high-voltage transistor device has a p-type semiconductor substrate that is furnished with a p-type epitaxial layer. A well and a body region are located in the epitaxial layer. A source region is arranged in the body region, and a drain region is arranged in the well. A channel region is located in the body region between the well and the source region. A gate electrode is arranged above the channel region. In the part of the semiconductor substrate and the epitaxial layer underneath the source region and the channel region, a deep body region is present, which has a higher dopant concentration in comparison to the remainder of the semiconductor substrate.
Opening claim text (preview).
The invention claimed is: 1. A high-voltage transistor device, comprising: a p-type semiconductor substrate provided with a p-type epitaxial layer; a high-voltage transistor, formed with an n-type well in the p-type epitaxial layer, a p-type body region in the p-type epitaxial layer, an n-type source region in the p-type body region, an n-type drain region in the n-type well, a channel region arranged in the p-type body region between the n-type well and the n-type sou…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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