Semiconductor wafer and its manufacture method, and semiconductor chip

Patent metadata

Field	Value
Publication number	US-9685416-B2
Application number	US-201414269840-A
Country	US
Kind code	B2
Filing date	May 5, 2014
Priority date	Mar 24, 2010
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between said first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of said first semiconductor chip area relative to said outer side wall of the lower metal layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate that includes a first semiconductor chip area formed with a semiconductor element;
laminated interlayer insulating films formed on the semiconductor substrate; and
a first metal ring formed in the laminated interlayer insulating films,
wherein:
the first metal ring has a multilayer structure of vertically stacked plural metal layers each of which consists of a uniformly-shaped contact layer or a uniformly-shaped wiring layer and each metal layer is disposed vertically between the semiconductor substrate and a top of the first metal ring;
the first metal ring has a closed loop-shape, and surrounds the semiconductor element;
the first metal ring has a first side wall;
the first metal ring has a second side wall on a side opposite to the first side wall;
the first metal ring includes a first lower metal layer and a first upper metal layer formed directly on the first lower metal layer;
the first metal ring includes a second lower metal layer formed directly under the first lower metal layer;
an end of the first upper metal layer on the first side wall is inwardly retracted from an end of the first lower metal layer on the first side wall near an edge of the first semiconductor chip area; and
an end of the first upper metal layer on the second side wall is farther from the edge of the first semiconductor chip area than an end of the second lower metal layer on the second side wall.

2. The semiconductor device according to claim 1 , further comprising:
an opening, that exposes a part of the first side wall, formed in the laminated interlayer insulating films.

3. The semiconductor device according to claim 1 , wherein:
the laminated interlayer insulating films include a cover insulating film that covers an uppermost metal layer of the first metal ring; and
an opening, that exposes an upper surface of the uppermost metal layer, is formed in the cover insulating film.

4. The semiconductor device according to claim 1 , further comprising
an insulating film formed in the substrate,
wherein
an outer end of the insulating film is located nearer to an edge of the first semiconductor chip area than the first side wall.

5. The semiconductor device according to claim 1 , wherein
the first lower metal layer includes copper; and
the first upper metal layer includes copper.

6. The semiconductor device according to claim 1 , wherein the laminated interlayer insulating films include a film that includes silicon, oxygen and carbon.

7. The semiconductor device according to claim 1 , wherein the first side wall is opposite to a side of the first metal ring that faces the semiconductor element.

8. The semiconductor device according to claim 1 , further comprising
a second metal ring, that surrounds the first metal ring, formed in the laminated interlayer insulating films.

9. The semiconductor device according to claim 8 , wherein:
the second metal ring includes a third side wall on an outer side;
the second metal ring includes a third lower metal layer and a second upper metal layer formed directly on the third lower metal layer; and
an end of the second upper metal layer on the third side wall is inwardly retracted from an end of the third lower metal layer on the third side wall near an edge of the first semiconductor chip area.

10. The semiconductor device according to claim 9 , wherein:
the laminated interlayer insulating films include a cover insulating film that covers an uppermost metal layer of the second metal ring; and
an opening, that exposes an upper surface of the uppermost metal layer, is formed in the cover insulating film.

11. The semiconductor device according to claim 9 , further comprising:
an opening, that exposes a part of the third side wall, formed in the laminated interlayer insulating films.

12. The semiconductor device according to claim 9 , wherein
the second lower metal layer includes copper; and
the second upper metal layer includes copper.

13. The semiconductor device according to claim 1 , wherein the laminated interlayer insulating films have an exposed top surface and cover at least part of an outer side surface of the first metal ring.

14. The semiconductor device according to claim 2 , wherein the laminated interlayer insulating films have an exposed top surface outside the first metal ring, and the opening formed in the laminated interlayer insulating films has a bottom surface which is common to the exposed top surface.

15. The semiconductor device according to claim 1 , wherein:
the first metal ring further includes a third upper metal layer formed directly on the first upper metal layer; and
an end of the third upper metal layer on the second side wall is farther from an edge of the first semiconductor chip area than an end of the first lower metal layer on the second side wall.

16. The semiconductor device according to claim 1 , wherein the first side wall of the first metal ring is generally inclined toward the semiconductor chip area.

17. The semiconductor device according to claim 16 , wherein in the first metal ring, upper portion is located nearer to the semiconductor chip area.

18. A semiconductor device comprising:
a semiconductor substrate that includes a first semiconductor chip area formed with a semiconductor element;
laminated interlayer insulating films formed on the semiconductor substrate;
a first metal ring having a closed loop-shape and formed in the laminated interlayer insulating films, including a lowermost metal layer formed on the semiconductor substrate along an edge of the semiconductor chip area; and
an insulating ring region having a closed loop-shape and embedded in the semiconductor substrate from an upper surface thereof, the insulating ring region being located along the edge of the semiconductor chip area;
wherein:
the first metal ring has an outer side wall and includes a first lower metal layer and a first upper metal layer formed directly on the first lower metal layer;
the lowermost metal layer contacts the insulating ring region; and
the insulating ring region has an outside edge outside the outer side wall of the lowermost metal layer;
the semiconductor device further comprising a crack formed in the semiconductor substrate from an outer side surface toward the semiconductor chip area, and arriving at an outer side surface of the insulating ring region.

19. The semiconductor device according to claim 18 , wherein the lowermost metal layer contacts a surface of the semiconductor substrate inside the insulating ring region.

20. The semiconductor device according to claim 18 , further comprising:
an isolation region formed in the semiconductor chip area,
wherein the isolation region and the insulating ring region are made of same material and have a same depth.

21. The semiconductor device according to claim 18 , wherein the crack further propagates along the outer side surface of the insulating ring region.

22. The semiconductor device according to claim 21 , wherein the crack further propagates along an interface between the insulating ring region and the lowermost layer of the laminated interlayer insulating films.

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Yoshizawa Kazutaka
• Ema Taiji

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic