Titanium tungsten liner used with copper interconnects

US9685370B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9685370-B2
Application numberUS-201414574889-A
CountryUS
Kind codeB2
Filing dateDec 18, 2014
Priority dateDec 18, 2014
Publication dateJun 20, 2017
Grant dateJun 20, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor structure, comprising: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; forming a via on the tungsten liner in the via opening; cleaning exposed surfaces in the via opening with buffered hydrofluoric acid; and maintaining a wafer comprising the wire in one or more chambers of a processing tool, without exposing the wafer to atmosphere, during the forming the via, the forming the titanium liner, and the forming the tungsten liner, wherein the via is a tungsten via that has a lower purity than that of the tungsten liner. 2. The method of claim 1 , wherein: the forming the titanium liner comprises a first ionized physical vapor deposition process; and the forming the tungsten liner comprises a second ionized physical vapor deposition process. 3. The method of claim 2 , further comprising performing the first ionized physical vapor deposition process and the second ionized physical vapor deposition process without an air break. 4. The method of claim 2 , wherein the forming the via comprises a tungsten chemical vapor deposition process. 5. The method of claim 1 , wherein the forming the via comprises filling the via opening with tungsten on the tungsten liner. 6. The method of claim 1 , wherein the titanium liner and the tungsten liner are devoid of nitride. 7. The method of claim 1 , further comprising heating the wafer to form a copper-titanium alloy region between the wire and the titanium liner. 8. The method of claim 1 , wherein the forming the via opening comprises forming a combined via and interconnect opening in a dual damascene process. 9. The method of claim 1 , wherein: the titanium liner is on and directly contacting the upper surface of the wire; the tungsten liner is on and directly contacting the titanium liner; and the via is on and directly contacting the tungsten liner. 10. The method of claim 9 , wherein: the titanium liner is pure titanium that is devoid of nitride; and the tungsten liner is pure tungsten that is devoid of nitride. 11. A method of forming a semiconductor structure, comprising: forming a copper wire in a first layer of dielectric material; forming a capping layer on the wire and the first layer of dielectric material; forming a second layer of dielectric material on the capping layer; etching a via opening in the second layer of dielectric material and the capping layer to expose an upper surface of the wire; forming a titanium liner in the via opening and on and directly contacting the upper surface of the wire; forming a tungsten liner in the via opening and on and directly contacting the titanium liner; and forming a tungsten via in the via opening and on and directly contacting the tungsten liner, wherein the tungsten via has a purity lower than a purity of the tungsten liner. 12. The method of claim 11 , wherein: the forming the titanium liner comprises depositing a layer of pure titanium using a first ionized physical vapor deposition process; and the forming the tungsten liner comprises depositing a layer of pure tungsten using a second ionized physical vapor deposition process. 13. The method of claim 12 , further comprising performing the first ionized physical vapor deposition process and the second ionized physical vapor deposition process without an air break. 14. The method of claim 11 , further comprising preventing nitrogen poisoning of the titanium liner. 15. The method of claim 11 , wherein the forming the tungsten via comprises filling the via opening with tungsten using a chemical vapor deposition process. 16. The method of claim 11 , further comprising forming a copper-titanium alloy region between the wire and the titanium liner. 17. A semiconductor structure, comprising: a copper wire in a first layer of dielectric material; a capping layer on and contacting the wire and the first layer of dielectric material; a second layer of dielectric material on the capping layer; a via opening extending through the second layer of dielectric material and the capping layer to an upper surface of the wire; a titanium liner in the via opening and on and contacting the upper surface of the wire; a tungsten liner in the via opening and on the titanium liner; and a tungsten via in the via opening and on the tungsten liner, wherein the titanium liner is pure titanium that is devoid of nitride; the tungsten liner is pure tungsten that is devoid of nitride; and the tungsten via has a lower purity than that of the tungsten liner. 18. The structure of claim 17 , wherein: the titanium liner directly contacts the wire; and the tungsten liner directly contacts both the titanium liner and the tungsten via. 19. The structure of claim 17 , further comprising a Cu—Ti alloy region between the titanium liner and the wire.

Assignees

Inventors

Classifications

  • Barrier, adhesion or liner layers · CPC title

  • by diffusing alloying elements · CPC title

  • comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

  • Vias, e.g. via plugs · CPC title

  • H10W20/035Primary

    combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

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Frequently asked questions

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What does patent US9685370B2 cover?
Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.
Who is the assignee on this patent?
IBM, Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/035. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 20 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).